Cross Reference: /src/sys/arch/arm/s3c2xx0/s3c2440

Lines Matching defs:dxs
188 		struct dmac_xfer_state *dxs;
191 		dxs = dc->dc_active;
192 		KASSERT(dxs != NULL);
194 		dx = &dxs->dxs_xfer;
197 			dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs--;
198 			if (dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs == 0) {
199 				dxs->dxs_complete = TRUE;
201 				dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg++;
205 			dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs--;
206 			if (dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs == 0) {
207 				dxs->dxs_complete = TRUE;
209 				dxs->dxs_segs[DMAC_DESC_DST].ds_curseg++;
213 		if (dxs->dxs_complete) {
214 			dxs->dxs_channel = DMAC_NO_CHANNEL;
228 			dmac_transfer_segment(channel, dxs);
277 	struct dmac_xfer_state *dxs;
279 	dxs = kmem_alloc(sizeof(struct dmac_xfer_state), KM_SLEEP);
281 	dxs->dxs_xfer.dx_done = NULL;
282 	dxs->dxs_xfer.dx_sync_bus = DMAC_SYNC_BUS_AUTO;
283 	dxs->dxs_xfer.dx_xfer_mode = DMAC_XFER_MODE_DEMAND;
284 	dxs->dxs_channel = DMAC_NO_CHANNEL;
286 	return ((dmac_xfer_t)dxs);
297 	struct dmac_xfer_state *dxs = (struct dmac_xfer_state*)dx;
302 	if (dxs->dxs_xfer.dx_peripheral != DMAC_PERIPH_NONE &&
303 	    dxs->dxs_xfer.dx_peripheral >= DMAC_N_PERIPH)
306 	dxs->dxs_complete = FALSE;
308 	perph = &s3c2440_peripherals[dxs->dxs_xfer.dx_peripheral];
310 	DPRINTF(("dp_id: %d, dx_peripheral: %d\n", perph->dp_id, dxs->dxs_xfer.dx_peripheral));
311 	KASSERT(perph->dp_id == dxs->dxs_xfer.dx_peripheral);
335 			dmac_start(channel_no, dxs);
347 		dxs->dxs_channel = channel_no;
348 		SIMPLEQ_INSERT_TAIL(&sc->sc_channels[channel_no].dc_queue, dxs, dxs_link);
358 dmac_start(uint8_t channel_no, struct dmac_xfer_state *dxs) {
366 	struct dmac_xfer		*dx = &dxs->dxs_xfer;
370 	DPRINTF(("Starting DMA transfer (%p) on channel %d\n", dxs, channel_no));
381 	dc->dc_active = dxs;
382 	dxs->dxs_channel = channel_no;
383 	dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg = dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs;
384 	dxs->dxs_segs[DMAC_DESC_SRC].ds_nsegs = dx->dx_desc[DMAC_DESC_SRC].xd_nsegs;
385 	dxs->dxs_segs[DMAC_DESC_DST].ds_curseg = dx->dx_desc[DMAC_DESC_DST].xd_dma_segs;
386 	dxs->dxs_segs[DMAC_DESC_DST].ds_nsegs = dx->dx_desc[DMAC_DESC_DST].xd_nsegs;
391 	if (dxs->dxs_xfer.dx_peripheral == DMAC_PERIPH_NONE) {
397 	switch (dxs->dxs_xfer.dx_xfer_mode) {
408 	sync_bus = dxs->dxs_xfer.dx_sync_bus;
410 	switch (dxs->dxs_xfer.dx_xfer_width) {
414 		dxs->dxs_width = 1;
419 		dxs->dxs_width = 2;
424 		dxs->dxs_width = 4;
430 	if (dxs->dxs_xfer.dx_peripheral == DMAC_PERIPH_NONE) {
435 		uint8_t source = s3c2440_peripherals[dxs->dxs_xfer.dx_peripheral].dp_channel_source[channel_no];
452 	dxs->dxs_options = options;
456 	dmac_transfer_segment(channel_no, dxs);
461 dmac_transfer_segment(uint8_t channel_no, struct dmac_xfer_state *dxs)
466 	struct dmac_xfer		*dx = &dxs->dxs_xfer;
473 			  dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr);
475 	DPRINTF(("Source address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_addr));
476 	DPRINTF(("Dest.  address: 0x%x\n", (unsigned)dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr));
493 			  dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_addr);
512 			transfer_size = dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_len;
514 			transfer_size = uimin(dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_len,
515 					    dxs->dxs_segs[DMAC_DESC_SRC].ds_curseg->ds_len);
519 			transfer_size = dxs->dxs_segs[DMAC_DESC_DST].ds_curseg->ds_len;
531 			  dxs->dxs_options |
532 dxs->dxs_width)+
533 				     uimin((transfer_size % dxs->dxs_width), 1))));
535 	DPRINTF(("Transfer size: %d (%d)\n", transfer_size, transfer_size/dxs->dxs_width));
539 	if (dxs->dxs_xfer.dx_peripheral == DMAC_PERIPH_NONE) {
590 		struct dmac_xfer_state *dxs;
592 		dxs = SIMPLEQ_FIRST(&dc->dc_queue);
595 		dmac_start(channel_no, dxs);
604 	struct dmac_xfer_state	  *dxs = (struct dmac_xfer_state*)dx;
607 	complete = dxs->dxs_complete;
621 		complete = dxs->dxs_complete;
627 	if (err == 0 && dxs->dxs_aborted == 1) {
639 	struct dmac_xfer_state		*dxs = (struct dmac_xfer_state*)dx;
643 	KASSERT(dxs->dxs_channel != (uint8_t)DMAC_NO_CHANNEL);
645 	dc = &sc->sc_channels[dxs->dxs_channel];
649 	if (dc->dc_active == dxs) {
653 				  DMA_MASKTRIG(dxs->dxs_channel),
656 				       DMA_MASKTRIG(dxs->dxs_channel));
657 		DPRINTF(("s3c2440_dma: channel %d mask trigger %x\n", dxs->dxs_channel, reg));
665 			dmac_channel_done(dxs->dxs_channel);
672 		SIMPLEQ_REMOVE(&dc->dc_queue, dxs, dmac_xfer_state, dxs_link);
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