Cross Reference: /src/sys/arch/arm/samsung/exynos5410

Lines Matching defs:eclk
521     struct exynos_clk *eclk)
527 	switch (eclk->type) {
545 	clk_parent = exynos5410_clock_get_parent(sc, &eclk->base);
549 	    eclk->base.name,
552 	    type, clk_get_rate(&eclk->base));
559 	struct exynos_clk *eclk;
568 	eclk = exynos5410_clock_find_by_id(clock_id);
569 	if (eclk)
570 		return &eclk->base;
577     struct exynos_clk *eclk)
579 	struct exynos_pll_clk *epll = &eclk->u.pll;
582 	KASSERT(eclk->type == EXYNOS_CLK_PLL);
584 	clk_parent = exynos5410_clock_find(eclk->parent);
596     struct exynos_clk *eclk, u_int rate)
604     struct exynos_clk *eclk, struct exynos_clk *eclk_parent)
606 	struct exynos_mux_clk *emux = &eclk->u.mux;
610 	KASSERT(eclk->type == EXYNOS_CLK_MUX);
631     struct exynos_clk *eclk)
633 	struct exynos_mux_clk *emux = &eclk->u.mux;
635 	KASSERT(eclk->type == EXYNOS_CLK_MUX);
647     struct exynos_clk *eclk)
649 	struct exynos_div_clk *ediv = &eclk->u.div;
652 	KASSERT(eclk->type == EXYNOS_CLK_DIV);
654 	clk_parent = exynos5410_clock_get_parent(sc, &eclk->base);
665     struct exynos_clk *eclk, u_int rate)
667 	struct exynos_div_clk *ediv = &eclk->u.div;
672 	KASSERT(eclk->type == EXYNOS_CLK_DIV);
674 	clk_parent = exynos5410_clock_get_parent(sc, &eclk->base);
697     struct exynos_clk *eclk, bool enable)
699 	struct exynos_gate_clk *egate = &eclk->u.gate;
701 	KASSERT(eclk->type == EXYNOS_CLK_GATE);
721 	struct exynos_clk *eclk;
723 	eclk = exynos5410_clock_find(name);
724 	if (eclk == NULL)
727 	atomic_inc_uint(&eclk->refcnt);
729 	return &eclk->base;
735 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
737 	KASSERT(eclk->refcnt > 0);
739 	atomic_dec_uint(&eclk->refcnt);
745 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
748 	switch (eclk->type) {
750 		return eclk->u.fixed.rate;
752 		return exynos5410_clock_get_rate_pll(priv, eclk);
758 		return exynos5410_clock_get_rate_div(priv, eclk);
760 		panic("exynos5410: unknown eclk type %d", eclk->type);
767 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
771 	switch (eclk->type) {
775 		return exynos5410_clock_set_rate_pll(priv, eclk, rate);
779 		return exynos5410_clock_set_rate_div(priv, eclk, rate);
783 		panic("exynos5410: unknown eclk type %d", eclk->type);
790 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
792 	switch (eclk->type) {
801 		return exynos5410_clock_enable_gate(priv, eclk, true);
803 		panic("exynos5410: unknown eclk type %d", eclk->type);
810 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
812 	switch (eclk->type) {
821 		return exynos5410_clock_enable_gate(priv, eclk, false);
823 		panic("exynos5410: unknown eclk type %d", eclk->type);
830 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
833 	switch (eclk->type) {
840 		return exynos5410_clock_set_parent_mux(priv, eclk, eclk_parent);
842 		panic("exynos5410: unknown eclk type %d", eclk->type);
849 	struct exynos_clk *eclk = (struct exynos_clk *)clk;
852 	switch (eclk->type) {
857 		if (eclk->parent != NULL) {
858 			eclk_parent = exynos5410_clock_find(eclk->parent);
862 		eclk_parent = exynos5410_clock_get_parent_mux(priv, eclk);
865 		panic("exynos5410: unknown eclk type %d", eclk->type);
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