Cross Reference: /src/sys/arch/arm/samsung/exynos

Lines Matching defs:bank
241 #define GPIO_WRITE(bank, reg, val) \
242 	bus_space_write_4((bank)->bank_sc->sc_bst, \
243 	    (bank)->bank_sc->sc_bsh, \
244 	    (bank)->bank_core_offset + (reg), (val))
245 #define GPIO_READ(bank, reg) \
246 	bus_space_read_4((bank)->bank_sc->sc_bst, \
247 	    (bank)->bank_sc->sc_bsh, \
248 	    (bank)->bank_core_offset + (reg))
254 	struct exynos_gpio_bank *bank = gba->gba_gc->gp_cookie;
255 	const char *bankname = bank->bank_name;
268 	struct exynos_gpio_bank * const bank = cookie;
271 	KASSERT(pin < bank->bank_bits);
272 	val = bus_space_read_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
281 	struct exynos_gpio_bank * const bank = cookie;
284 	KASSERT(pin < bank->bank_bits);
285 	val = bus_space_read_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
290 	bus_space_write_1(bank->bank_sc->sc_bst, bank->bank_sc->sc_bsh,
297 	struct exynos_gpio_bank * const bank = cookie;
320 	exynos_gpio_pin_ctl_write(bank, &ncfg, pin);
323 void exynos_gpio_pin_ctl_write(const struct exynos_gpio_bank *bank,
330 		val = GPIO_READ(bank, EXYNOS_GPIO_CON);
333 		GPIO_WRITE(bank, EXYNOS_GPIO_CON, val);
337 		val = GPIO_READ(bank, EXYNOS_GPIO_PUD);
340 		GPIO_WRITE(bank, EXYNOS_GPIO_PUD, val);
344 		val = GPIO_READ(bank, EXYNOS_GPIO_DRV);
347 		GPIO_WRITE(bank, EXYNOS_GPIO_DRV, val);
351 		val = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
354 		GPIO_WRITE(bank, EXYNOS_GPIO_CONPWD, val);
358 		val = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
361 		GPIO_WRITE(bank, EXYNOS_GPIO_PUDPWD, val);
375 	struct exynos_gpio_bank *bank =
377 	if (bank == NULL) {
378 		aprint_error_dev(parent->sc_dev, "no bank found for %s\n",
386 	sc->sc_bank = bank;
388 	gc_tag = &bank->bank_gc;
389 	gc_tag->gp_cookie = bank;
394 	gba.gba_gc = &bank->bank_gc;
395 	gba.gba_pins = bank->bank_pins;
396 	gba.gba_npins = bank->bank_bits;
398 	bank->bank_sc = sc;
399 	bank->bank_dev =
403 	bank->bank_cfg.cfg = GPIO_READ(bank, EXYNOS_GPIO_CON);
404 	bank->bank_cfg.pud = GPIO_READ(bank, EXYNOS_GPIO_PUD);
405 	bank->bank_cfg.drv = GPIO_READ(bank, EXYNOS_GPIO_DRV);
406 	bank->bank_cfg.conpwd = GPIO_READ(bank, EXYNOS_GPIO_CONPWD);
407 	bank->bank_cfg.pudpwd = GPIO_READ(bank, EXYNOS_GPIO_PUDPWD);
409 	fdtbus_register_gpio_controller(bank->bank_dev, node,
423 	struct exynos_gpio_bank *bank;
426 		bank = &epb->epb_banks[n];
427 		if (!strncmp(bank->bank_name, name,
428 			     strlen(bank->bank_name))) {
429 			return bank;
456 	struct exynos_gpio_bank *bank = NULL;
471 			bank = &epb->epb_banks[n];
475 	KASSERTMSG(bank != NULL, "no such gpio bank child of %s @ %p: %s @ %p",
479 	gpin->pin_sc = bank->bank_sc;
480 	gpin->pin_bank = bank;
485 	exynos_gpio_pin_ctl(bank, gpin->pin_no, gpin->pin_flags);
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