Cross Reference: /src/sys/arch/arm/sociox/if

Lines Matching defs:CSR_WRITE
546 #define CSR_WRITE(sc,off,val) \
620 	CSR_WRITE(sc, MACCMD, reg | CMD_BUSY);
629 	CSR_WRITE(sc, MACDATA, val);
630 	CSR_WRITE(sc, MACCMD, reg | CMD_IOWR | CMD_BUSY);
1021 	CSR_WRITE(sc, TDBA_LO, BUS_ADDR_LO32(p));
1022 	CSR_WRITE(sc, TDBA_HI, BUS_ADDR_HI32(p));
1023 	CSR_WRITE(sc, RDBA_LO, BUS_ADDR_LO32(q));
1024 	CSR_WRITE(sc, RDBA_HI, BUS_ADDR_HI32(q));
1025 	CSR_WRITE(sc, TXCONF, DESCNF_LE);	/* little endian */
1026 	CSR_WRITE(sc, RXCONF, DESCNF_LE);	/* little endian */
1027 	CSR_WRITE(sc, DMACTL_TMR, sc->sc_freq / 1000000 - 1);
1031 	CSR_WRITE(sc, xINTSR, IRQ_UCODE); /* pre-cautional W1C */
1032 	CSR_WRITE(sc, CORESTAT, 0);	  /* start uengine to reprogram */
1037 	CSR_WRITE(sc, xINTSR, IRQ_UCODE); /* W1C load complete report */
1041 	CSR_WRITE(sc, DMACTL_M2H, M2H_MODE_TRANS);
1042 	CSR_WRITE(sc, PKTCTRL, MODENRM); /* change to use normal mode */
1048 	CSR_WRITE(sc, TXISR, ~0);	/* clear pending emtpry/error irq */
1049 	CSR_WRITE(sc, xINTAE_CLR, ~0);	/* disable tx / rx interrupts */
1113 	CSR_WRITE(sc, RXIE_CLR, ~0);
1114 	CSR_WRITE(sc, TXIE_CLR, ~0);
1115 	CSR_WRITE(sc, xINTAE_CLR, ~0);
1116 	CSR_WRITE(sc, TXISR, ~0);
1117 	CSR_WRITE(sc, RXISR, ~0);
1181 	CSR_WRITE(sc, DESC_SRST, 01);
1184 	CSR_WRITE(sc, DESC_INIT, 01);
1191 	CSR_WRITE(sc, FLOWTHR, (48<<16) | 36);	/* pause|resume threshold */
1194 	CSR_WRITE(sc, INTF_SEL, sc->sc_miigmii ? INTF_GMII : INTF_RGMII);
1196 	CSR_WRITE(sc, RXCOALESC, 8);		/* Rx coalesce bound */
1197 	CSR_WRITE(sc, TXCOALESC, 8);		/* Tx coalesce bound */
1198 	CSR_WRITE(sc, RCLSCTIME, 500);		/* Rx co. guard time usec */
1199 	CSR_WRITE(sc, TCLSCTIME, 500);		/* Tx co. guard time usec */
1201 	CSR_WRITE(sc, RXIE_SET, RXI_RC_ERR | RXI_PKTCNT | RXI_TMREXP);
1202 	CSR_WRITE(sc, TXIE_SET, TXI_TR_ERR | TXI_TXDONE | TXI_TMREXP);
1203 	CSR_WRITE(sc, xINTAE_SET, IRQ_RX | IRQ_TX);
1461 		CSR_WRITE(sc, TXSUBMIT, 1);
1538 		CSR_WRITE(sc, xINTAE_CLR, (IRQ_TX | IRQ_RX));
1541 		CSR_WRITE(sc, RXISR, status);
1550 		CSR_WRITE(sc, TXISR, status);
1558 		CSR_WRITE(sc, xINTAE_SET, (IRQ_TX | IRQ_RX));
1841 		CSR_WRITE(sc, DMACTL_H2M, DMACTL_STOP);
1842 		CSR_WRITE(sc, DMACTL_M2H, DMACTL_STOP);
1846 	CSR_WRITE(sc, SWRESET, 0);		/* reset operation */
1847 	CSR_WRITE(sc, SWRESET, SRST_RUN);	/* manifest run */
1848 	CSR_WRITE(sc, COMINIT, INIT_DB | INIT_CLS);
1908 		CSR_WRITE(sc, port, ucode);
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