Lines Matching refs:sunxi_ccu_reset
107 static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = {
108 SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30),
110 SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16),
112 SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16),
114 SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16),
116 SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16),
118 SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16),
120 SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16),
122 SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16),
124 SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16),
126 SUNXI_CCU_RESET(H6_RST_BUS_MSGBOX, MSGBOX_BGR_REG, 16),
128 SUNXI_CCU_RESET(H6_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16),
130 SUNXI_CCU_RESET(H6_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16),
132 SUNXI_CCU_RESET(H6_RST_BUS_DBG, DBGSYS_BGR_REG, 16),
134 SUNXI_CCU_RESET(H6_RST_BUS_PSI, PSI_BGR_REG, 16),
136 SUNXI_CCU_RESET(H6_RST_BUS_PWM, PWM_BGR_REG, 16),
140 SUNXI_CCU_RESET(H6_RST_BUS_DRAM, DRAM_CLK_REG, 30),
142 SUNXI_CCU_RESET(H6_RST_BUS_NAND, NAND_BGR_REG, 16),
144 SUNXI_CCU_RESET(H6_RST_BUS_MMC0, SMHC_BGR_REG, 16),
145 SUNXI_CCU_RESET(H6_RST_BUS_MMC1, SMHC_BGR_REG, 17),
146 SUNXI_CCU_RESET(H6_RST_BUS_MMC2, SMHC_BGR_REG, 18),
148 SUNXI_CCU_RESET(H6_RST_BUS_UART0, UART_BGR_REG, 16),
149 SUNXI_CCU_RESET(H6_RST_BUS_UART1, UART_BGR_REG, 17),
150 SUNXI_CCU_RESET(H6_RST_BUS_UART2, UART_BGR_REG, 18),
151 SUNXI_CCU_RESET(H6_RST_BUS_UART3, UART_BGR_REG, 19),
153 SUNXI_CCU_RESET(H6_RST_BUS_I2C0, TWI_BGR_REG, 16),
154 SUNXI_CCU_RESET(H6_RST_BUS_I2C1, TWI_BGR_REG, 17),
155 SUNXI_CCU_RESET(H6_RST_BUS_I2C2, TWI_BGR_REG, 18),
156 SUNXI_CCU_RESET(H6_RST_BUS_I2C3, TWI_BGR_REG, 19),
158 SUNXI_CCU_RESET(H6_RST_BUS_SCR0, SCR_BGR_REG, 16),
159 SUNXI_CCU_RESET(H6_RST_BUS_SCR1, SCR_BGR_REG, 17),
161 SUNXI_CCU_RESET(H6_RST_BUS_SPI0, SPI_BGR_REG, 16),
162 SUNXI_CCU_RESET(H6_RST_BUS_SPI1, SPI_BGR_REG, 17),
164 SUNXI_CCU_RESET(H6_RST_BUS_EMAC, EMAC_BGR_REG, 16),
166 SUNXI_CCU_RESET(H6_RST_BUS_TS, TS_BGR_REG, 16),
168 SUNXI_CCU_RESET(H6_RST_BUS_IR_TX, CIRTX_BGR_REG, 16),
170 SUNXI_CCU_RESET(H6_RST_BUS_THS, THS_BGR_REG, 16),
172 SUNXI_CCU_RESET(H6_RST_BUS_I2S0, I2S_PCM_BGR_REG, 16),
173 SUNXI_CCU_RESET(H6_RST_BUS_I2S1, I2S_PCM_BGR_REG, 17),
174 SUNXI_CCU_RESET(H6_RST_BUS_I2S2, I2S_PCM_BGR_REG, 18),
175 SUNXI_CCU_RESET(H6_RST_BUS_I2S3, I2S_PCM_BGR_REG, 19),
177 SUNXI_CCU_RESET(H6_RST_BUS_SPDIF, OWA_BGR_REG, 16),
179 SUNXI_CCU_RESET(H6_RST_BUS_DMIC, DMIC_BGR_REG, 16),
181 SUNXI_CCU_RESET(H6_RST_BUS_AUDIO_HUB, AUDIO_HUB_BGR_REG, 16),
183 SUNXI_CCU_RESET(H6_RST_USB_PHY0, USB0_CLK_REG, 30),
185 SUNXI_CCU_RESET(H6_RST_USB_PHY1, USB1_CLK_REG, 30),
187 SUNXI_CCU_RESET(H6_RST_USB_PHY3, USB3_CLK_REG, 30),
188 SUNXI_CCU_RESET(H6_RST_USB_HSIC, USB3_CLK_REG, 28),
190 SUNXI_CCU_RESET(H6_RST_BUS_OHCI0, USB_BGR_REG, 16),
191 SUNXI_CCU_RESET(H6_RST_BUS_OHCI3, USB_BGR_REG, 19),
192 SUNXI_CCU_RESET(H6_RST_BUS_EHCI0, USB_BGR_REG, 20),
193 SUNXI_CCU_RESET(H6_RST_BUS_XHCI, USB_BGR_REG, 21),
194 SUNXI_CCU_RESET(H6_RST_BUS_EHCI3, USB_BGR_REG, 23),
195 SUNXI_CCU_RESET(H6_RST_BUS_OTG, USB_BGR_REG, 24),
197 SUNXI_CCU_RESET(H6_RST_BUS_PCIE, PCIE_BGR_REG, 16),
198 SUNXI_CCU_RESET(H6_RST_PCIE_POWERUP, PCIE_BGR_REG, 17),
200 SUNXI_CCU_RESET(H6_RST_BUS_HDMI, HDMI_BGR_REG, 16),
201 SUNXI_CCU_RESET(H6_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17),
203 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TOP, DISPLAY_IF_TOP_BGR_REG, 16),
205 SUNXI_CCU_RESET(H6_RST_BUS_TCON_LCD0, TCON_LCD_BGR_REG, 16),
207 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TV0, TCON_TV_BGR_REG, 16),
209 SUNXI_CCU_RESET(H6_RST_BUS_CSI, CSI_BGR_REG, 16),
211 SUNXI_CCU_RESET(H6_RST_BUS_HDCP, HDMI_HDCP_BGR_REG, 16),
Indexes created Thu Oct 23 18:09:57 GMT 2025