Lines Matching refs:SUNXI_CCU_GATE
114 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc",
212 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb",
214 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb",
216 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb",
218 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb",
220 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb",
222 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb",
224 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb",
226 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb",
228 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb",
230 SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb",
232 SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb",
234 SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb",
236 SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb",
238 SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb",
242 SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb",
244 SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb",
246 SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb",
248 SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb",
250 SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb",
252 SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb",
254 SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb",
258 SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0",
260 SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0",
262 SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0",
266 SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1",
268 SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1",
270 SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1",
272 SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1",
274 SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1",
278 SUNXI_CCU_GATE(A13_CLK_CODEC, "codec", "pll_audio",
282 SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m",
284 SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m",
286 SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m",
Indexes created Mon Oct 20 20:10:13 GMT 2025