Lines Matching defs:HDMI_WRITE
102 #define HDMI_WRITE(sc, reg, val) \
250 HDMI_WRITE(sc, j, 0);
342 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
348 HDMI_WRITE(sc, SUNXI_HDMI_DDC_SLAVE_ADDR_REG, val);
352 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, val);
354 HDMI_WRITE(sc, SUNXI_HDMI_DDC_BYTE_COUNTER_REG, len);
356 HDMI_WRITE(sc, SUNXI_HDMI_DDC_COMMAND_REG, type);
360 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG, val);
391 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_FIFO_CTRL_REG, val);
397 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_SLAVE_ADDR_REG, val);
399 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_COMMAND_REG,
405 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG, val);
453 HDMI_WRITE(sc, SUNXI_HDMI_DDC_FIFO_CTRL_REG, 0);
454 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CTRL_REG,
466 HDMI_WRITE(sc, SUNXI_HDMI_DDC_CLOCK_REG,
470 HDMI_WRITE(sc, SUNXI_HDMI_DDC_DBG_REG, 0x300);
472 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,
476 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CLOCK_REG,
480 HDMI_WRITE(sc, SUNXI_A31_HDMI_DDC_CTRL_REG,
618 HDMI_WRITE(sc, SUNXI_HDMI_CTRL_REG, SUNXI_HDMI_CTRL_MODULE_EN);
621 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0xfe800000);
622 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x00d8c830);
624 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, 0x7e80000f);
625 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, 0x01ded030);
627 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, dbg0_reg);
825 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);
862 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, 0xffffffff);
918 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL0_REG, pad_ctrl0);
919 HDMI_WRITE(sc, SUNXI_HDMI_PAD_CTRL1_REG, pad_ctrl1);
920 HDMI_WRITE(sc, SUNXI_HDMI_PLL_CTRL_REG, pll_ctrl);
924 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (0<<21));
927 HDMI_WRITE(sc, SUNXI_HDMI_PLL_DBG0_REG, (1<<21));
952 HDMI_WRITE(sc, SUNXI_HDMI_VID_CTRL_REG, val);
958 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_0_REG, val);
964 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_1_REG, val);
970 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_2_REG, val);
976 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_3_REG, val);
987 HDMI_WRITE(sc, SUNXI_HDMI_VID_TIMING_4_REG, val);
990 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT0_REG, 0);
991 HDMI_WRITE(sc, SUNXI_HDMI_GP_PKT1_REG, 0);
992 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL0_REG, 0x00005321);
993 HDMI_WRITE(sc, SUNXI_HDMI_PKT_CTRL1_REG, 0x0000000f);
1010 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);
1031 HDMI_WRITE(sc, SUNXI_HDMI_ADMA_CTRL_REG, val);
1041 HDMI_WRITE(sc, SUNXI_HDMI_AUD_FMT_REG, val);
1044 HDMI_WRITE(sc, SUNXI_HDMI_AUD_PCM_CTRL_REG, 0x76543210);
1049 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTS_REG, cts);
1050 HDMI_WRITE(sc, SUNXI_HDMI_AUD_N_REG, n);
1055 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS0_REG, val);
1064 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CH_STATUS1_REG, val);
1069 HDMI_WRITE(sc, SUNXI_HDMI_AUD_CTRL_REG, val);
1152 HDMI_WRITE(sc, SUNXI_HDMI_INT_STATUS_REG, intsts);
Indexes created Thu Oct 02 14:10:14 GMT 2025