Cross Reference: /src/sys/arch/arm/sunxi/sunxi_mc

Lines Matching defs:cluster
55 #define	 PRCM_CL_RST_CTRL(cluster)	(0x4 + (cluster) * 0x4)
56 #define	 PRCM_CL_PWROFF(cluster)	(0x100 + (cluster) * 0x4)
57 #define	 PRCM_CL_PWR_CLAMP(cluster, cpu) (0x140 + (cluster) * 0x10 + (cpu) * 0x4)
63 #define	 CPUCFG_CL_RST(cluster)		(0x30 + (cluster) * 0x4)
69 #define	 CPUXCFG_CL_RST(cluster)	(0x80 + (cluster) * 0x4)
76 #define	 CPUXCFG_CL_CTRL0(cluster)	(0x0 + (cluster) * 0x10)
77 #define	 CPUXCFG_CL_CTRL1(cluster)	(0x4 + (cluster) * 0x10)
115     bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu, enum sunxi_mc_soc soc,
122 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
124 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
128 		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
130 		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
135 		val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster));
137 		bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster), val);
142 		bus_space_write_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu), 0xff >> i);
146 		if (bus_space_read_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu)) == 0)
150 		printf("CPU %#llx failed to start\n", __SHIFTIN(cluster, MPIDR_AFF1) | __SHIFTIN(cpu, MPIDR_AFF0));
155 	val = bus_space_read_4(bst, prcm, PRCM_CL_PWROFF(cluster));
161 		val &= ~__BIT(0);	/* cluster power gate */
164 		val &= ~__BIT(4);	/* cluster power gate */
166 	bus_space_write_4(bst, prcm, PRCM_CL_PWROFF(cluster), val);
169 	val = bus_space_read_4(bst, prcm, PRCM_CL_RST_CTRL(cluster));
171 	bus_space_write_4(bst, prcm, PRCM_CL_RST_CTRL(cluster), val);
174 		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
176 		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
181 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
191 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
194 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster));
196 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster), val);
208 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
225 	error = sunxi_mc_smp_start(bst, prcm, cpucfg, cpuxcfg, cluster, cpu,
242 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
258 	error = sunxi_mc_smp_start(bst, prcm, 0, cpuxcfg, cluster, cpu,
259 	    MC_SOC_A80, cluster == 0 ? MC_CORE_CA7 : MC_CORE_CA15);
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