Lines Matching refs:sc_regh
67 bus_space_handle_t sc_regh;
212 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_regh) != 0) {
228 sz = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE);
230 sz = bus_space_read_4(sc->sc_iot, sc->sc_regh,
234 sz = bus_space_read_4(sc->sc_iot, sc->sc_regh,
239 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE, sz);
255 bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_REVISION));
321 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG);
325 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG, reg);
327 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_SYSCONFIG,
331 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG, reg);
335 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GLOBAL_ALPHA,
338 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_VID1_BASE_0,
340 bus_space_write_4(sc->sc_iot, sc->sc_regh,
342 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_VID1_SIZE,
344 bus_space_write_4(sc->sc_iot, sc->sc_regh,
347 bus_space_write_4(sc->sc_iot, sc->sc_regh,
349 bus_space_write_4(sc->sc_iot, sc->sc_regh,
351 bus_space_write_4(sc->sc_iot, sc->sc_regh,
353 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_VID1_ATTRIBUTES,
360 bus_space_write_4(sc->sc_iot, sc->sc_regh,
368 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_BASE_0,
370 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_TABLE_BASE,
372 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE,
374 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_POSITION,
376 bus_space_write_4(sc->sc_iot, sc->sc_regh,
378 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_ATTRIBUTES,
385 printf("dss_control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
387 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_CONTROL,
398 bus_space_write_4(sc->sc_iot, sc->sc_regh, adr,
402 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_VENC_F_CONTROL,
404 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_VENC_SYNC_CTRL,
407 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_DEFAULT_COLOR_1,
412 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);
413 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
417 printf("attr: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
419 printf("preload: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
421 printf("config: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
423 printf("control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
425 printf("dss_control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
427 printf("threshold: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
429 printf("GFX size: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
431 printf("row inc: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
433 printf("pixel inc: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh,
796 bus_space_write_4(sc->sc_iot, sc->sc_regh,
803 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);
804 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
827 bus_space_write_4(sc->sc_iot, sc->sc_regh,
831 bus_space_write_4(sc->sc_iot, sc->sc_regh,
842 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);
843 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
847 bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG));
1150 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_BASE_0,
1152 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_POSITION,
1154 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE,
1156 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_ROW_INC,
1162 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);
1163 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
1180 bus_space_write_4(sc->sc_iot, sc->sc_regh,
1231 reg = bus_space_read_4(sc->sc_iot, sc->sc_regh,
1233 bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
Indexes created Sun Oct 19 02:09:48 GMT 2025