Lines Matching refs:sc_iwin
121 (0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
123 sc->sc_iwin[0].iwin_xlate);
126 PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo);
128 PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi);
130 sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
132 sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
134 sc->sc_iwin[0].iwin_base_lo =
135 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
139 (0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
143 PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo);
145 PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi);
147 sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st,
149 sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st,
151 sc->sc_iwin[1].iwin_base_lo =
152 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
156 (0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
158 sc->sc_iwin[2].iwin_xlate);
161 PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo);
163 PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi);
165 sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st,
167 sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st,
169 sc->sc_iwin[2].iwin_base_lo =
170 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
174 (0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
176 sc->sc_iwin[3].iwin_xlate);
179 ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
181 ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
183 sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st,
185 sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st,
187 sc->sc_iwin[3].iwin_base_lo =
188 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo);
209 sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo;
210 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
319 dr->dr_sysbase = sc->sc_iwin[2].iwin_xlate;
320 dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
321 dr->dr_len = sc->sc_iwin[2].iwin_size;