Cross Reference: /src/sys/arch/arm/xscale/ixp425

Lines Matching defs:regAddr
203 		uint32_t regAddr, uint32_t regSize,
206 		uint32_t regAddr, uint32_t regVal,
209 		uint32_t regAddr, uint32_t regValue, int verify);
667     uint32_t regAddr;
702     uint32_t regAddr;
768     for (regAddr = 0;
769 	 regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG && error == 0;
770 	 regAddr++) {
772 	error = npe_physical_reg_write(sc, regAddr, 0, true);
806 	    ixNpeDlEcsRegResetValues[i].regAddr,
813     for (regAddr = IX_NPEDL_REG_OFFSET_EXCT;
814 	 regAddr <= IX_NPEDL_REG_OFFSET_AP3;
815 	 regAddr += sizeof(uint32_t))
816 	npe_reg_write(sc, regAddr, 0);
1095     uint32_t regAddr, uint32_t regSize,
1118     /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
1119     npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
1120 	(regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
1126 	    __func__, regAddr, regSize, ctxtNum, error);
1139 npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal,
1145 	__func__, regAddr, regVal, regSize, ctxtNum);
1149 	error = npe_logical_reg_write(sc, regAddr,
1157 		     regAddr + sizeof(uint16_t),
1176 	npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
1192 	    __func__, regAddr, regVal, regSize, ctxtNum, error);
1198     	error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum, &retRegVal);
1214     uint32_t regAddr, uint32_t regValue, int verify)
1219      * Set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
1223 	       (regAddr >> IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
1226 	/* regAddr = 0 or 4  */
1227 	regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
1229 	error = npe_logical_reg_write(sc, regAddr, regValue,
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