Cross Reference: /src/sys/arch/arm/xscale/ixp425

Lines Matching defs:qi
270 	    struct qmgrInfo *qi = &sc->qinfo[i];
272 	    qi->cb = dummyCallback;
273 	    qi->priority = IX_QMGR_Q_PRIORITY_0;	/* default priority */
280 	    qi->intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
289 	    qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
290 	    qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
291 	    qi->qConfigRegAddr = IX_QMGR_Q_CONFIG_ADDR_GET(i);
296 		qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET +
301 		qi->qUflowStatBitMask = 
307 		qi->qOflowStatBitMask = 
313 		qi->qStatRegAddr = IX_QMGR_QUELOWSTAT0_OFFSET +
318 		qi->qStatBitsOffset =
322 		qi->qUOStatRegAddr = 0;		/* XXX */
325 		qi->qStat0BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
328 		qi->qStat1BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
358 	struct qmgrInfo *qi = &sc->qinfo[qId];
364 	qi->qSizeInWords = qEntries;
366 	qi->qReadCount = 0;
367 	qi->qWriteCount = 0;
368 	qi->qSizeInEntries = qEntries;	/* XXX kept for code clarity */
372 	    qi->cb = dummyCallback;
373 	    qi->cbarg = 0;
375 	    qi->cb = cb;
376 	    qi->cbarg = cbarg;
384 	sc->aqmFreeSramAddress += (qi->qSizeInWords * sizeof(uint32_t));
402 	struct qmgrInfo *qi = &sc->qinfo[qId];
405 	    __func__, qId, entry, qi->qWriteCount, qi->qSizeInEntries);
408 	aqm_reg_write(sc, qi->qAccRegAddr, entry);
412 	    int qSize = qi->qSizeInEntries;
417 	    if (qi->qWriteCount++ == qSize) {	/* check for overflow */
418 		uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
425 		if ((status & qi->qOflowStatBitMask) ||
426 		    ((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) {
430 		    aqm_reg_write(sc, qi->qUOStatRegAddr,
431 			status & ~qi->qOflowStatBitMask);
432 		    qi->qWriteCount = qSize;
445 		qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr);
457 		    qi->qWriteCount = qSize;
460 		    qi->qWriteCount = qPtrs & (qSize - 1);
471 	struct qmgrInfo *qi = &sc->qinfo[qId];
472 	bus_size_t off = qi->qAccRegAddr;
480 	qi->qReadCount = 0;
485 	    uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
487 	    if (status & qi->qUflowStatBitMask) { /* clear underflow status */
488 		aqm_reg_write(sc, qi->qUOStatRegAddr,
489 		    status &~ qi->qUflowStatBitMask);
500 	struct qmgrInfo *qi = &sc->qinfo[qId];
502 	bus_size_t off = qi->qAccRegAddr;
519 	qi->qReadCount = 0;
524 	    uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
526 	    if (status & qi->qUflowStatBitMask) { /* clear underflow status */
527 		aqm_reg_write(sc, qi->qUOStatRegAddr,
528 		    status &~ qi->qUflowStatBitMask);
541 	const struct qmgrInfo *qi = &sc->qinfo[qId];
546 	    status = aqm_reg_read(sc, qi->qStatRegAddr);
549 	    status = (status >> qi->qStatBitsOffset) & QLOWSTATMASK;
552 	    if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT0_OFFSET)&qi->qStat0BitMask)
554 	    if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT1_OFFSET)&qi->qStat1BitMask)
673 	struct qmgrInfo *qi;
683 		qi = &sc->qinfo[q];
684 		if (qi->priority == pri) { 
691 			    qi->intRegCheckMask;
698 		qi = &sc->qinfo[q];
699 		if (qi->priority == pri) {
706 			    qi->intRegCheckMask;
754 	struct qmgrInfo *qi;
777 		 qi = &sc->qinfo[qIndex];
778 		 if (intRegVal == qi->intRegCheckMask) {
783 		    qi->cb(qIndex, qi->cbarg);
807 			 qi = &sc->qinfo[qIndex];
810 			 if (intRegVal & qi->intRegCheckMask) {
812 			     qi->cb(qIndex, qi->cbarg);
814 			     intRegVal &= ~qi->intRegCheckMask;
839 	struct qmgrInfo *qi = &qinfo[qId];
845 		qi->statusCheckValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
846 		qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
849 		qi->statusCheckValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
850 		qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
853 		qi->statusCheckValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
854 		qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
857 		qi->statusCheckValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
858 		qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK;
861 		qi->statusCheckValue = 0;
862 		qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
865 		qi->statusCheckValue = 0;
866 		qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
869 		qi->statusCheckValue = 0;
870 		qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
873 		qi->statusCheckValue = 0;
874 		qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK;
891 	    qi->statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
893 	    qi->statusCheckValue <<= shiftVal;
894 	    qi->statusMask <<= shiftVal;
897 	    qi->statusWordOffset = 0;
901 	    qi->statusMask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
902 	    qi->statusCheckValue = qi->statusMask;
980 	const struct qmgrInfo *qi = &sc->qinfo[qId];
987 	     | ((toAqmBufferSize(qi->qSizeInWords) & IX_QMGR_SIZE_MASK) <<
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