Cross Reference: /src/sys/arch/arm/xscale/pxa2x0

Lines Matching refs:ad
72 #define KERNADDR(ad) ((void *)((ad)->ad_addr))
635 	struct acu_dma *ad;
638 	ad = kmem_alloc(sizeof(*ad), KM_SLEEP);
641 	if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer()) == NULL)
644 	ad->ad_size = size;
646 	error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs,
647 	    ACU_N_SEGS, &ad
651 	error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size,
652 	    &ad->ad_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
657 	    BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ad->ad_map);
661 	error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size,
664 		bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
665 unmap_dmamem:	bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size);
666 free_dmamem:	bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
667 free_xfer:	pxa2x0_dmac_free_xfer(ad->ad_dx);
668 error:		kmem_free(ad, sizeof(*ad));
672 	ad->ad_dx->dx_cookie = sc;
673 	ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH;
674 	ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4;
675 	ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32;
677 	ad->ad_next = sc->sc_dmas;
678 	sc->sc_dmas = ad;
679 	return (KERNADDR(ad));
686 	struct acu_dma *ad, **adp;
688 	for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) {
689 		if (KERNADDR(ad) == ptr) {
690 			pxa2x0_dmac_abort_xfer(ad->ad_dx);
691 			pxa2x0_dmac_free_xfer(ad->ad_dx);
692 			ad->ad_segs[0].ds_len = ad->ad_size;	/* XXX */
693 			bus_dmamap_unload(sc->sc_dmat, ad->ad_map);
694 			bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
695 			bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size);
696 			bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
697 			*adp = ad->ad_next;
698 			kmem_free(ad, sizeof(*ad));
755 	struct acu_dma *ad;
764 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
766 	if (ad == NULL) {
771 	sc->sc_txdma = ad;
772 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
773 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
780 	dx = ad->ad_dx;
786 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
787 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
811 	struct acu_dma *ad;
820 	for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
822 	if (ad == NULL) {
827 	sc->sc_rxdma = ad;
828 	ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
829 	ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
836 	dx = ad->ad_dx;
842 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
843 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
866 	struct acu_dma *ad;
868 	if ((ad = sc->sc_txdma) == NULL)
871 	if (ad->ad_dx != dx)
889 	struct acu_dma *ad;
891 	if ((ad = sc->sc_rxdma) == NULL)
894 	if (ad->ad_dx != dx)
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