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Lines Matching defs:gh

255 	struct gpio_irq_handler *gh;
283 	gh = kmem_alloc(sizeof(*gh), KM_SLEEP);
284 	gh->gh_func = func;
285 	gh->gh_arg = arg;
286 	gh->gh_spl = spl;
287 	gh->gh_gpio = gpio;
288 	gh->gh_level = level;
289 	gh->gh_next = sc->sc_handlers[gpio];
290 	sc->sc_handlers[gpio] = gh;
327 	return (gh);
334 	struct gpio_irq_handler *gh = cookie;
337 	bit = GPIO_BIT(gh->gh_gpio);
339 	reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio));
341 	pxagpio_reg_write(sc, GPIO_REG(GPIO_GFER0, gh->gh_gpio), reg);
342 	reg = pxagpio_reg_read(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio));
344 	pxagpio_reg_write(sc, GPIO_REG(GPIO_GRER0, gh->gh_gpio), reg);
346 	pxagpio_reg_write(sc, GPIO_REG(GPIO_GEDR0, gh->gh_gpio), bit);
348 	sc->sc_mask[GPIO_BANK(gh->gh_gpio)] &= ~bit;
349 	sc->sc_handlers[gh->gh_gpio] = NULL;
351 	if (gh->gh_gpio == 0) {
359 	if (gh->gh_gpio == 1) {
368 	kmem_free(gh, sizeof(*gh));
411 	struct gpio_irq_handler **ghp, *gh;
458 		if ((gh = *ghp) == NULL) {
465 		s = _splraise(gh->gh_spl);
467 			nhandled = (gh->gh_func)(gh->gh_arg);
469 			gh = gh->gh_next;
470 		} while (gh != NULL);
661 	struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v;
663 	pxa2x0_gpio_set_intr_level(gh->gh_gpio, IPL_NONE);
672 	struct gpio_irq_handler *gh = (struct gpio_irq_handler *)v;
674 	pxa2x0_gpio_set_intr_level(gh->gh_gpio, gh->gh_level);