Cross Reference: /src/sys/arch/arm/xscale/pxa2x0

Lines Matching defs:dx
43 	struct dmac_xfer *dx;
183 	struct dmac_xfer *dx;
188 	dx = pxa2x0_dmac_allocate_xfer();
189 	if (dx == NULL) {
192 	p->dx = dx;
215 	dx->dx_cookie = sc;
216 	dx->dx_priority = DMAC_PRIORITY_NORMAL;
217 	dx->dx_dev_width = DMAC_DEV_WIDTH_4;
218 	dx->dx_burst_size = DMAC_BURST_SIZE_32;
232 	pxa2x0_dmac_free_xfer(dx);
246 			pxa2x0_dmac_abort_xfer(p->dx);
247 			pxa2x0_dmac_free_xfer(p->dx);
287 		pxa2x0_dmac_abort_xfer(sc->sc_txdma->dx);
300 		pxa2x0_dmac_abort_xfer(sc->sc_rxdma->dx);
313 	struct dmac_xfer *dx;
338 	dx = p->dx;
339 	dx->dx_done = pxa2x0_i2s_dmac_ointr;
340 	dx->dx_peripheral = DMAC_PERIPH_I2STX;
341 	dx->dx_flow = DMAC_FLOW_CTRL_DEST;
342 	dx->dx_loop_notify = DMAC_DONT_LOOP;
343 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
344 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = p->nsegs;
345 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = p->segs;
346 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
347 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
348 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
354 	return pxa2x0_dmac_start_xfer(dx);
363 	struct dmac_xfer *dx;
388 	dx = p->dx;
389 	dx->dx_done = pxa2x0_i2s_dmac_iintr;
390 	dx->dx_peripheral = DMAC_PERIPH_I2SRX;
391 	dx->dx_flow = DMAC_FLOW_CTRL_SRC;
392 	dx->dx_loop_notify = DMAC_DONT_LOOP;
393 	dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
394 	dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
395 	dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
396 	dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
397 	dx->dx_desc[DMAC_DESC_DST].xd_nsegs = p->nsegs;
398 	dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = p->segs;
404 	return pxa2x0_dmac_start_xfer(dx);
408 pxa2x0_i2s_dmac_ointr(struct dmac_xfer *dx, int status)
410 	struct pxa2x0_i2s_softc *sc = dx->dx_cookie;
415 	if (sc->sc_txdma->dx != dx) {
431 pxa2x0_i2s_dmac_iintr(struct dmac_xfer *dx, int status)
433 	struct pxa2x0_i2s_softc *sc = dx->dx_cookie;
438 	if (sc->sc_rxdma->dx != dx) {
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