Lines Matching defs:PCLK
116 #define PCLK (8053976) /* PCLK pin input clock rate */
117 #define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */
166 PCLK/16, /* BRgen, PCLK, divisor 16 */
171 PCLK/16, /* BRgen, PCLK, divisor 16 */
181 PCLK/16, /* BRgen, PCLK, divisor 16 */
186 PCLK/16, /* BRgen, PCLK, divisor 16 */
196 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */
201 PCLK_HD/16, /* BRgen, PCLK, divisor 16 */
209 * other machines, assume only PCLK is available
211 PCLK/16, /* BRgen, PCLK, divisor 16 */
216 PCLK/16, /* BRgen, PCLK, divisor 16 */
1206 case 0: /* BRgen, PCLK */