Cross Reference: /src/sys/arch/atari/dev/zs.c

Lines Matching refs:zc
292 	struct zschan *zc;
308 		cs->cs_zc = zc =
313 		(void)zc->zc_csr;
314 		(void)zc->zc_csr;
320 			ZS_WRITE(zc, 9, ZSWR9_HARD_RESET);
322 			ZS_WRITE(zc, 9, 0);
328 		zs_loadchannelregs(zc, zs_init_regs);
593 	struct zschan *zc;
607 			zc = cs0->cs_zc;
610 			    (v = zsrint(cs0, zc)) != 0) {
615 			    (v = zsxint(cs0, zc)) != 0) {
620 			    (v = zssint(cs0, zc)) != 0) {
628 			zc = cs1->cs_zc;
631 			    (v = zsrint(cs1, zc)) != 0) {
636 			    (v = zsxint(cs1, zc)) != 0) {
641 			    (v = zssint(cs1, zc)) != 0) {
656 zsrint(struct zs_chanstate *cs, struct zschan *zc)
664 	c = ZS_READ(zc, 1);
665 	c |= (zc->zc_data << 8);
668 	zc->zc_csr = ZSWR0_RESET_ERRORS;
669 	zc->zc_csr = ZSWR0_CLR_INTR;
675 zsxint(struct zs_chanstate *cs, struct zschan *zc)
680 		zc->zc_csr = ZSWR0_RESET_TXINT;
681 		zc->zc_csr = ZSWR0_CLR_INTR;
685 	zc->zc_data = *cs->cs_tba++;
686 	zc->zc_csr = ZSWR0_CLR_INTR;
691 zssint(struct zs_chanstate *cs, struct zschan *zc)
695 	rr0 = zc->zc_csr;
696 	zc->zc_csr = ZSWR0_RESET_STATUS;
697 	zc->zc_csr = ZSWR0_CLR_INTR;
709 			ZS_WRITE(zc, 3, cs->cs_creg[3]);
714 			ZS_WRITE(zc, 3, cs->cs_creg[3]);
743 	struct zschan *zc;
759 		zc     = cs->cs_zc;
803 					c = zc->zc_csr;
808 					zs_loadchannelregs(zc, cs->cs_creg);
814 						zc->zc_data = *cs->cs_tba++;
1317 zs_loadchannelregs(struct zschan *zc, uint8_t *reg)
1321 	zc->zc_csr = ZSM_RESET_ERR;	/* reset error condition */
1322 	i = zc->zc_data;		/* drain fifo */
1323 	i = zc->zc_data;
1324 	i = zc->zc_data;
1325 	ZS_WRITE(zc,  4, reg[4]);
1326 	ZS_WRITE(zc, 10, reg[10]);
1327 	ZS_WRITE(zc,  3, reg[3] & ~ZSWR3_RX_ENABLE);
1328 	ZS_WRITE(zc,  5, reg[5] & ~ZSWR5_TX_ENABLE);
1329 	ZS_WRITE(zc,  1, reg[1]);
1330 	ZS_WRITE(zc,  9, reg[9]);
1331 	ZS_WRITE(zc, 11, reg[11]);
1332 	ZS_WRITE(zc, 12, reg[12]);
1333 	ZS_WRITE(zc, 13, reg[13]);
1334 	ZS_WRITE(zc, 14, reg[14]);
1335 	ZS_WRITE(zc, 15, reg[15]);
1336 	ZS_WRITE(zc,  3, reg[3]);
1337 	ZS_WRITE(zc,  5, reg[5]);
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