Lines Matching refs:mfb
47 volatile u_char mfb[__MR(24)-1]; /* Sparse */
50 #define mf_gpip mfb[__MR(0) ] /* gen-purp I/O interrupt port */
51 #define mf_aer mfb[__MR(1) ] /* active edge register */
52 #define mf_ddr mfb[__MR(2) ] /* data direction register */
53 #define mf_iera mfb[__MR(3) ] /* interrupt enable register A */
54 #define mf_ierb mfb[__MR(4) ] /* interrupt enable register B */
55 #define mf_ipra mfb[__MR(5) ] /* interrupt pending register A */
56 #define mf_iprb mfb[__MR(6) ] /* interrupt pending register B */
57 #define mf_isra mfb[__MR(7) ] /* interrupt in-service register A */
58 #define mf_isrb mfb[__MR(8) ] /* interrupt in-service register B */
59 #define mf_imra mfb[__MR(9) ] /* interrupt mask register A */
60 #define mf_imrb mfb[__MR(10)] /* interrupt mask register B */
61 #define mf_vr mfb[__MR(11)] /* vector register */
62 #define mf_tacr mfb[__MR(12)] /* timer control register A */
63 #define mf_tbcr mfb[__MR(13)] /* timer control register B */
64 #define mf_tcdcr mfb[__MR(14)] /* timer control register C+D */
65 #define mf_tadr mfb[__MR(15)] /* timer data register A */
66 #define mf_tbdr mfb[__MR(16)] /* timer data register B */
67 #define mf_tcdr mfb[__MR(17)] /* timer data register C */
68 #define mf_tddr mfb[__MR(18)] /* timer data register D */
69 #define mf_scr mfb[__MR(19)] /* synchronous character register */
70 #define mf_ucr mfb[__MR(20)] /* USART control register */
71 #define mf_rsr mfb[__MR(21)] /* receiver status register */
72 #define mf_tsr mfb[__MR(22)] /* transmitter status register */
73 #define mf_udr mfb[__MR(23)] /* USART data register */
Indexes created Mon Sep 29 21:09:56 GMT 2025