Lines Matching refs:ba
79 tseng_init(pci_chipset_tag_t pc, pcitag_t tag, int id, volatile uint8_t *ba,
107 et6000_init(ba, fb, i);
118 vgaw(ba, GREG_MISC_OUTPUT_W, 0x63);
119 vgaw(ba, GREG_VIDEOSYSENABLE, 0x01);
120 WCrt(ba, 0x17 , 0x00); /* color */
121 WCrt(ba, 0x11 , 0x00); /* color */
122 vgaw(ba, VDAC_MASK , 0xff);
123 WSeq(ba, SEQ_ID_RESET , 0x00);
124 vgaw(ba, GREG_HERCULESCOMPAT, 0x03);
125 vgaw(ba, GREG_DISPMODECONTROL, 0xa0);
129 WSeq(ba, i, seq_tab[i]);
130 WSeq(ba, SEQ_ID_RESET , 0x03);
132 vgar(ba, VDAC_ADDRESS); /* clear old state */
133 vgar(ba, VDAC_MASK);
134 vgar(ba, VDAC_MASK);
135 vgar(ba, VDAC_MASK);
136 vgar(ba, VDAC_MASK);
137 vgaw(ba, VDAC_MASK, 0); /* set to palette */
138 vgar(ba, VDAC_ADDRESS); /* clear state */
139 vgaw(ba, VDAC_MASK, 0xff);
144 WCrt(ba, CRT_ID_END_VER_RETR, (RCrt(ba, CRT_ID_END_VER_RETR) & 0x7f));
148 WCrt(ba, i, crt_tab[i]);
152 WGfx(ba, i, gfx_tab[i]);
155 WAttr(ba, i, i);
157 WAttr(ba, i, attr_tab[i - 0x10]);
158 WAttr(ba, 0x20, 0);
168 et6000_init(volatile uint8_t *ba, uint8_t *fb, int iter)
177 ba += 0x800;
179 ba[0x40] = 0x06; /* Use standard vga addressing */
180 ba[0x41] = 0x2a; /* Performance control */
181 ba[0x43] = 0x02; /* XCLK/SCLK config */
182 ba[0x44] = ras_cas_tab[iter]; /* RAS/CAS config */
183 ba[0x46] = 0x00; /* CRT display feature */
184 ba[0x47] = 0x10;
185 ba[0x58] = 0x00; /* Video Control 1 */
186 ba[0x59] = 0x04; /* Video Control 2 */
191 ba[0x42] = 0x00; /* MCLK == CLK0 */
192 ba[0x67] = 0x00; /* Start filling from dac-reg 0 and up... */
194 ba[0x69] = dac_tab[i];
196 if (ba[8] == 0x70) { /* et6100, right? */
204 bv = ba[45];
205 ba[0x45] = bv | 0x40; /* Reset MDRAM's */
206 ba[0x45] = bv | 0x70; /* Program latency value */
208 ba[0x45] = bv; /* Back to normal */
Indexes created Sat Oct 11 16:09:52 GMT 2025