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Lines Matching defs:asich

134 	bus_space_handle_t asich, asich1, memh;
170 	    0, &asich) != 0) {
186 	    (vaddr_t)bus_space_vaddr(asict, asich);
189 	if (bus_space_peek_1(asict, asich, WE_PROM + 0) == 0 ||
190 	    bus_space_peek_1(asict, asich, WE_PROM + 1) == 0)
200 		reg = bus_space_read_1(asict, asich, WE_PROM + i);
213 	bus_space_write_1(asict, asich, WE_MSR, WE_MSR_RST);
216 	bus_space_write_1(asict, asich, WE_MSR,
217 	    bus_space_read_1(asict, asich, WE_MSR) & ~WE_MSR_RST);
225 	type = bus_space_read_1(asict, asich, WE_CARD_ID);
230 	hwr = bus_space_read_1(asict, asich, WE790_HWR);
231 	bus_space_write_1(asict, asich, WE790_HWR, hwr | WE790_HWR_SWH);
232 	switch (bus_space_read_1(asict, asich, WE790_RAR) & WE790_RAR_SZ64) {
249 	bus_space_write_1(asict, asich, WE790_HWR, hwr);
268 	hwr = bus_space_read_1(asict, asich, WE790_HWR);
269 	bus_space_write_1(asict, asich, WE790_HWR, hwr | WE790_HWR_SWH);
271 	reg = bus_space_read_1(asict, asich, WE790_GCR);
274 	bus_space_write_1(asict, asich, WE790_HWR, hwr & ~WE790_HWR_SWH);
293 		bus_space_unmap(asict, asich, WE_NPORTS);
309 	bus_space_handle_t nich, asich, asich1, memh;
325 	if (bus_space_map(asict, va->va_iobase, WE_NPORTS, 0, &asich) != 0) {
336 	    (vaddr_t)bus_space_vaddr(asict, asich);
338 	if (bus_space_subregion(asict, asich, WE_NIC_OFFSET, WE_NIC_NPORTS,
351 	wsc->sc_asich = asich;
380 	bus_space_write_1(asict, asich, WE790_ICR,
381 	    bus_space_read_1(asict, asich, WE790_ICR) | WE790_ICR_EIL);
403 		bus_space_unmap(asict, asich, WE_NPORTS);