Lines Matching refs:outb
364 outb(FDC_RATE(ctlr), un->un_type->rate); /* rate set */
409 outb(FDC_DATA(ctlr), cmd);
459 outb(FDC_DOR(ctlr), DOR_RESET | DOR_DMAEN | unit
468 outb(FDC_DOR(ctlr), DOR_RESET); /* reset & motor off */
477 outb(FDC_DOR(ctlr), 0); /* fdc reset */
479 outb(FDC_DOR(ctlr), DOR_RESET);
656 outb(INT_CTL0, ICW1_AT); /* ICW1 */
657 outb(INT_CTL1, 0); /* ICW2 for master */
658 outb(INT_CTL1, (1 << CASCADE_IRQ)); /* ICW3 tells slaves */
659 outb(INT_CTL1, ICW4_AT); /* ICW4 */
661 outb(INT_CTL1, (INT_MASK = ~(1 << CASCADE_IRQ)));
664 outb(INT2_CTL0, ICW1_AT); /* ICW1 */
665 outb(INT2_CTL1, 8); /* ICW2 for slave */
666 outb(INT2_CTL1, CASCADE_IRQ); /* ICW3 is slave nr */
667 outb(INT2_CTL1, ICW4_AT); /* ICW4 */
669 outb(INT2_CTL1, (INT2_MASK = ~0)); /* IRQ 8-15 mask */
685 outb(irc_no ? INT2_CTL1 : INT_CTL1, ~(1 << (irq_no >> (irc_no * 3))));
688 outb(irc_no ? INT2_CTL0 : INT_CTL0, OCW3_PL);
701 outb(INT2_CTL0, OCW2_CLEAR | (irq_no >> 3));
702 outb(INT_CTL0, OCW2_CLEAR | CASCADE_IRQ);
704 outb(INT_CTL0, OCW2_CLEAR | irq_no);
707 outb(INT_CTL1, INT_MASK);
708 outb(INT2_CTL1, INT2_MASK);
742 outb(DMA_RESET, 0);
744 outb(DMA_DEVCON, 0x00);
745 outb(DMA_INIT, DMA_RESET_VAL); /* reset the dma controller */
747 outb(DMA_MODE, func == F_READ ? DMA_READ : DMA_WRITE);
748 outb(DMA_FLIPFLOP, 0); /* write anything to reset it */
750 outb(DMA_ADDR, (int)pbuf >> 0);
751 outb(DMA_ADDR, (int)pbuf >> 8);
752 outb(DMA_LTOP, (int)pbuf >> 16);
753 outb(DMA_HTOP, (int)pbuf >> 24);
755 outb(DMA_COUNT, (size - 1) >> 0);
756 outb(DMA_COUNT, (size - 1) >> 8);
757 outb(DMA_INIT, chan); /* some sort of enable */
Indexes created Wed Oct 22 13:09:56 GMT 2025