Cross Reference: /src/sys/arch/cesfic/dev/zs.c

Lines Matching refs:cs
106 	struct zs_chanstate *cs;
124 			cs = &zs_conschan_store;
126 			cs = kmem_zalloc(sizeof(*cs), KM_SLEEP);
128 				cs->cs_reg_csr  = base + 7;
129 				cs->cs_reg_data = base + 15;
131 				cs->cs_reg_csr  = base + 3;
132 				cs->cs_reg_data = base + 11;
134 			memcpy(cs->cs_creg, zs_init_reg, 16);
135 			memcpy(cs->cs_preg, zs_init_reg, 16);
136 			cs->cs_defspeed = 9600;
138 		zsc->zsc_cs[channel] = cs;
139 		zs_lock_init(cs);
141 		cs->cs_defcflag = CREAD | CS8 | HUPCL;
144 		cs->cs_rr0_dcd = ZSRR0_DCD;
145 		cs->cs_rr0_cts = 0;
146 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
147 		cs->cs_wr5_rts = 0;
149 		cs->cs_channel = channel;
150 		cs->cs_private = NULL;
151 		cs->cs_ops = &zsops_null;
152 		cs->cs_brg_clk = 4000000 / 16;
160 			zs_write_reg(cs, 9, 0);
173 			zs_write_reg(cs,  9, reset);
214 zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
218 	*cs->cs_reg_csr = reg;
220 	val = *cs->cs_reg_csr;
226 zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
228 	*cs->cs_reg_csr = reg;
230 	*cs->cs_reg_csr = val;
235 zs_read_csr(struct zs_chanstate *cs)
239 	val = *cs->cs_reg_csr;
245 zs_write_csr(struct zs_chanstate *cs, uint8_t val)
248 	*cs->cs_reg_csr = val;
253 zs_read_data(struct zs_chanstate *cs)
257 	val = *cs->cs_reg_data;
263 zs_write_data(struct zs_chanstate *cs, uint8_t val)
266 	*cs->cs_reg_data = val;
271 zs_set_speed(struct zs_chanstate *cs, int bps)
275 	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
282 	int real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
287 	cs->cs_preg[12] = tconst;
288 	cs->cs_preg[13] = tconst >> 8;
294 zs_set_modes(struct zs_chanstate *cs, int cflag)
308 		cs->cs_rr0_dcd = 0;
309 		cs->cs_preg[15] &= ~ZSWR15_DCD_IE;
312 		cs->cs_rr0_dcd = ZSRR0_DCD;
313 		cs->cs_preg[15] |= ZSWR15_DCD_IE;
317 		cs->cs_wr5_dtr = ZSWR5_DTR;
318 		cs->cs_wr5_rts = ZSWR5_RTS;
319 		cs->cs_rr0_cts = ZSRR0_CTS;
320 		cs->cs_preg[15] |= ZSWR15_CTS_IE;
322 		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
323 		cs->cs_wr5_rts = 0;
324 		cs->cs_rr0_cts = 0;
325 		cs->cs_preg[15] &= ~ZSWR15_CTS_IE;
337 zs_abort(struct zs_chanstate *cs)
344 		rr0 = *cs->cs_reg_csr;
358 	struct zs_chanstate *cs = arg;
366 		rr0 = *cs->cs_reg_csr;
371 	stat = zs_read_reg(cs, 1) & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE);
373 		zs_write_csr(cs, ZSM_RESET_ERR);
378 	c = *cs->cs_reg_data;
391 	struct zs_chanstate *cs = arg;
398 		rr0 = *cs->cs_reg_csr;
402 	*cs->cs_reg_data = c;
410 	struct zs_chanstate *cs = &zs_conschan_store;
413 	c = zs_getc(cs);
420 	struct zs_chanstate *cs = &zs_conschan_store;
422 	zs_putc(cs, c);
431 	struct zs_chanstate *cs;
437 	cs = &zs_conschan_store;
441 	cs->cs_reg_csr  = (uint8_t *)base + 7;
442 	cs->cs_reg_data = (uint8_t *)base + 15;
445 	memcpy(cs->cs_preg, zs_init_reg, 16);
446 	cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS);
450 	/* cs->cs_defspeed = zs_get_speed(cs); */
451 	cs->cs_defspeed = 9600;	/* XXX */
454 	zs_write_reg(cs, 9, 0);
457 	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
460 	zs_loadchannelregs(cs);
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