Lines Matching refs:ISSET
268 if (!ISSET(pi->pi_flags, PLC_FLAG_32BIT_ACCESS))
278 if (!ISSET(pi->pi_flags, PLC_FLAG_32BIT_ACCESS))
288 if (!ISSET(pi->pi_flags, PLC_FLAG_32BIT_ACCESS)) {
302 if (!ISSET(pi->pi_flags, PLC_FLAG_32BIT_ACCESS)) {
317 if (!ISSET(pi->pi_flags, PLC_FLAG_32BIT_ACCESS)) {
389 ISSET(tp->t_cflag, CLOCAL) ? "+" : "-",
390 ISSET(sc->sc_msr, PL01X_MSR_DCD) ? "+" : "-",
391 ISSET(tp->t_state, TS_CARR_ON) ? "+" : "-",
392 ISSET(sc->sc_mcr, PL01X_MCR_DTR) ? "+" : "-",
397 ISSET(tp->t_cflag, CRTSCTS) ? "+" : "-",
398 ISSET(sc->sc_msr, PL01X_MSR_CTS) ? "+" : "-",
399 ISSET(tp->t_state, TS_TTSTOP) ? "+" : "-",
400 ISSET(sc->sc_mcr, PL01X_MCR_RTS) ? "+" : "-",
569 if (ISSET(sc->sc_hwflags, PLCOM_HW_TXFIFO_DISABLE)) {
592 if (ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE)) {
610 if (!ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE)) {
658 if (ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE|PLCOM_HW_KGDB))
756 if (ISSET(tp->t_cflag, HUPCL)) {
765 if (ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE)) {
816 if (sc == NULL || !ISSET(sc->sc_hwflags, PLCOM_HW_DEV_OK) ||
829 if (ISSET(sc->sc_hwflags, PLCOM_HW_KGDB))
843 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
910 if (ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE)) {
919 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
921 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
923 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
962 error = ttyopen(tp, PLCOMDIALOUT(dev), ISSET(flag, O_NONBLOCK));
973 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
992 if (!ISSET(tp->t_state, TS_ISOPEN))
1001 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
1313 if (ISSET(ttybits, TIOCM_DTR))
1315 if (ISSET(ttybits, TIOCM_RTS))
1350 if (ISSET(plcombits, PL01X_MCR_DTR))
1352 if (ISSET(plcombits, PL01X_MCR_RTS))
1356 if (ISSET(plcombits, PL01X_MSR_DCD))
1358 if (ISSET(plcombits, PL01X_MSR_CTS))
1360 if (ISSET(plcombits, PL01X_MSR_DSR))
1362 if (ISSET(plcombits, PL011_MSR_RI))
1376 switch (ISSET(cflag, CSIZE)) {
1390 if (ISSET(cflag, PARENB)) {
1392 if (!ISSET(cflag, PARODD))
1395 if (ISSET(cflag, CSTOPB))
1433 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1434 ISSET(sc->sc_hwflags, PLCOM_HW_CONSOLE)) {
1448 lcr = ISSET(sc->sc_lcr, PL01X_LCR_BRK) | cflag2lcr(t->c_cflag);
1457 if (ISSET(sc->sc_hwflags, PLCOM_HW_FIFO))
1486 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1494 if (ISSET(t->c_cflag, CRTSCTS)) {
1509 } else if (ISSET(t->c_cflag, MDMBUF)) {
1532 if (ISSET(sc->sc_mcr, PL01X_MCR_DTR))
1578 if (!ISSET(t->c_cflag, CHWFLOW)) {
1582 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1586 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) {
1602 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, PL01X_MSR_DCD));
1609 if (!ISSET(t->c_cflag, CHWFLOW)) {
1633 while (! ISSET(PREAD1(pi, PL01XCOM_FR), PL01X_FR_RXFE)
1712 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1717 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1721 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1742 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1776 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1804 if (!ISSET(sc->sc_cr, PL010_CR_TIE)) {
1811 if (!ISSET(sc->sc_imsc, PL011_INT_TX)) {
1842 if (ISSET(tp->t_state, TS_BUSY)) {
1846 if (!ISSET(tp->t_state, TS_TTSTOP))
1896 if (ISSET(rsr, PL01X_RSR_ERROR)) {
1897 if (ISSET(rsr, PL01X_RSR_OE)) {
1903 if (ISSET(rsr, PL01X_RSR_BE | PL01X_RSR_FE))
1905 if (ISSET(rsr, PL01X_RSR_PE))
1912 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1948 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1964 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
1978 if (ISSET(tp->t_state, TS_FLUSH))
1996 if (ISSET(delta, sc->sc_msr_dcd)) {
2000 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, PL01X_MSR_DCD));
2003 if (ISSET(delta, sc->sc_msr_cts)) {
2005 if (ISSET(msr, sc->sc_msr_cts)) {
2055 ret = ISSET(stat, PL010_IIR_IMASK);
2060 ret = ISSET(stat, PL011_INT_ALLMASK);
2102 if (!ISSET(fr, PL01X_FR_RXFE) &&
2103 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
2109 if (ISSET(rsr, PL01X_RSR_ERROR))
2112 if (ISSET(rsr, PL01X_RSR_BE)) {
2119 if (ISSET(sc->sc_hwflags,
2133 if (ISSET(fr, PL01X_FR_RXFE))
2145 if (ISSET(fr, PL01X_FR_RXFE))
2157 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
2164 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
2193 rxintr = ISSET(istatus, PL010_IIR_RIS);
2203 rxintr = ISSET(istatus, PL011_INT_RX);
2229 msintr = ISSET(istatus, PL010_IIR_MIS);
2236 msintr = ISSET(istatus, PL011_INT_MSMASK);
2291 if (ISSET(delta, sc->sc_msr_mask)) {
2298 if (ISSET(~msr, sc->sc_msr_mask)) {
2318 txintr = ISSET(istatus, PL010_IIR_TIS);
2321 txintr = ISSET(istatus, PL011_INT_TX);
2357 if (ISSET(sc->sc_cr, PL010_CR_TIE)) {
2365 if (ISSET(sc->sc_imsc, PL011_INT_TX)) {
2428 if (ISSET(PREAD1(pi, PL01XCOM_FR), PL01X_FR_RXFE)) {
2452 && !ISSET(stat = PREAD1(pi, PL01XCOM_FR), PL01X_FR_RXFE)) {
2461 while (ISSET(PREAD1(pi, PL01XCOM_FR), PL01X_FR_TXFF) && --timo)
Indexes created Wed Oct 22 13:09:56 GMT 2025