Cross Reference: /src/sys/arch/evbarm/dev/plcom.c

Lines Matching refs:SET
111  * We need to know if cn_check_magic triggered debugger, so set a flag.
443 	SET(sc->sc_mcr, PL01X_MCR_DTR | PL01X_MCR_RTS);
445 	/* Turn on line break interrupt, set carrier. */
448 		SET(sc->sc_cr, PL010_CR_RIE | PL010_CR_RTIE);
459 		SET(sc->sc_cr, PL011_CR_RXE | PL011_CR_TXE);
460 		SET(sc->sc_cr, PL011_MCR(sc->sc_mcr));
498 		SET(sc->sc_hwflags, PLCOM_HW_CONSOLE);
499 		SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
508 			SET(sc->sc_cr, PL011_CR_RXE | PL011_CR_TXE);
575 		SET(sc->sc_hwflags, PLCOM_HW_FIFO);
613 			SET(sc->sc_hwflags, PLCOM_HW_KGDB);
635 	SET(sc->sc_hwflags, PLCOM_HW_DEV_OK);
739 	SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
742 	/* Clear any break condition set with TIOCSBRK. */
772 			SET(sc->sc_cr, PL010_CR_RIE | PL010_CR_RTIE);
776 			SET(sc->sc_cr, PL011_CR_RXE);
777 			SET(sc->sc_imsc, PL011_INT_RT | PL011_INT_RX);
783 		SET(sc->sc_cr, PL010_CR_RIE | PL010_CR_RTIE);
788 		SET(sc->sc_cr, PL011_CR_RXE | PL011_CR_TXE);
789 		SET(sc->sc_imsc, PL011_INT_RT | PL011_INT_RX);
882 			SET(sc->sc_cr,
889 			SET(sc->sc_cr, PL011_CR_RXE | PL011_CR_TXE);
890 			SET(sc->sc_imsc, PL011_INT_RT | PL011_INT_RX |
920 			SET(t.c_cflag, CLOCAL);
922 			SET(t.c_cflag, CRTSCTS);
924 			SET(t.c_cflag, MDMBUF);
1271 		SET(sc->sc_lcr, PL01X_LCR_BRK);
1293 		SET(sc->sc_mcr, sc->sc_mcr_dtr);
1314 		SET(plcombits, PL01X_MCR_DTR);
1316 		SET(plcombits, PL01X_MCR_RTS);
1324 		SET(sc->sc_mcr, plcombits);
1329 		SET(sc->sc_mcr, plcombits);
1351 		SET(ttybits, TIOCM_DTR);
1353 		SET(ttybits, TIOCM_RTS);
1357 		SET(ttybits, TIOCM_CD);
1359 		SET(ttybits, TIOCM_CTS);
1361 		SET(ttybits, TIOCM_DSR);
1363 		SET(ttybits, TIOCM_RI);
1366 		SET(ttybits, TIOCM_LE);
1378 		SET(lcr, PL01X_LCR_5BITS);
1381 		SET(lcr, PL01X_LCR_6BITS);
1384 		SET(lcr, PL01X_LCR_7BITS);
1387 		SET(lcr, PL01X_LCR_8BITS);
1391 		SET(lcr, PL01X_LCR_PEN);
1393 			SET(lcr, PL01X_LCR_EPS);
1396 		SET(lcr, PL01X_LCR_STP2);
1435 		SET(t->c_cflag, CLOCAL);
1463 		SET(sc->sc_lcr, PL01X_LCR_FEN);
1491 	 * Set the flow control pins depending on the current flow control
1506 			SET(sc->sc_cr, PL011_CR_CTSEN | PL011_CR_RTSEN);
1525 		 * If no flow control, then always set RTS.  This will make
1533 			SET(sc->sc_mcr, PL01X_MCR_RTS);
1549 		SET(sc->sc_mcr, sc->sc_mcr_dtr);
1691 		SET(sc->sc_cr, PL011_MCR(sc->sc_mcr_active));
1713 			SET(sc->sc_rx_flags, RX_TTY_BLOCKED);
1746 		SET(sc->sc_mcr, sc->sc_mcr_rts);
1747 		SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1759 		SET(sc->sc_cr, PL011_MCR(sc->sc_mcr_active));
1798 	SET(tp->t_state, TS_BUSY);
1805 			SET(sc->sc_cr, PL010_CR_TIE);
1812 			SET(sc->sc_imsc, PL011_INT_TX);
1847 			SET(tp->t_state, TS_FLUSH);
1904 				SET(code, TTY_FE);
1906 				SET(code, TTY_PE);
1932 				SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1952 					SET(sc->sc_cr,
1958 					SET(sc->sc_imsc,
2166 				SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
2175 				SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
2292 			SET(sc->sc_msr_delta, delta);
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