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Lines Matching defs:REG_WR

83 #define REG_WR(reg, val)						\
246 		REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU,
265 	REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000);
266 	REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN);
267 	REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0);
327         REG_WR(PWR_VDDIOCTRL, tmp_r);
333         REG_WR(PWR_VDDIOCTRL, tmp_r);
342         REG_WR(PWR_VDDIOCTRL, tmp_r);
346         REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ);
350         REG_WR(PWR_VDDIOCTRL, tmp_r);
366         REG_WR(CLKCTRL_SSP, tmp_r);
374         REG_WR(CLKCTRL_SSP, tmp_r);
403         REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP);