Lines Matching refs:r0
62 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */
63 bic r0, r0, #CPU_CONTROL_MMU_ENABLE
64 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE
65 orr r0, r0, #CPU_CONTROL_DC_ENABLE
66 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE
67 bic r0, r0, #CPU_CONTROL_BEND_ENABLE
68 orr r0, r0, #CPU_CONTROL_SYST_ENABLE
69 bic r0, r0, #CPU_CONTROL_ROM_ENABLE
70 orr r0, r0, #CPU_CONTROL_IC_ENABLE
71 bic r0, r0, #CPU_CONTROL_VECRELOC
72 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */
79 mov r0, #0
80 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
83 mov r0, #0x00000001 /* use domain 0 as client */
84 mcr p15, 0, r0, c3, c0 ,0 /* write domain */
87 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */
88 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */
91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
94 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */
95 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */
98 mov r0, #0
99 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0
102 mov r0, #0
103 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */
104 mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 */
105 mcr p15, 0, r0, c15, c2 ,0 /* DBMR = 0 */
106 mcr p15, 0, r0, c15, c3 ,0 /* DBCR = 0 (never watch) */
107 mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */
129 ldr r0, Ltable
135 str r3, [r0], #4
143 ldr r0, Ltable
144 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */
149 str r3, [r0]
152 ldr r0, Ltable
153 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */
154 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */
157 ldr r0, Lstart
171 mov pc, r0 /* leap to kernel entry point! */
Indexes created Thu Nov 06 21:09:53 GMT 2025