Lines Matching defs:tmp_r
94 uint32_t tmp_r;
96 tmp_r = REG_RD(PWR_5VCTRL);
97 tmp_r &= ~HW_POWER_5VCTRL_VBUSVALID_TRSH;
98 tmp_r |= __SHIFTIN(VBUSVALID_TRSH, HW_POWER_5VCTRL_VBUSVALID_TRSH);
99 REG_WR(PWR_5VCTRL, tmp_r);
125 uint32_t tmp_r;
137 tmp_r = REG_RD(PWR_DCLIMITS);
138 tmp_r &= ~HW_POWER_DCLIMITS_POSLIMIT_BUCK;
139 tmp_r |= __SHIFTIN(0x30, HW_POWER_DCLIMITS_POSLIMIT_BUCK);
140 REG_WR(PWR_DCLIMITS, tmp_r);
150 uint32_t tmp_r;
154 tmp_r = REG_RD(PWR_DCDC4P2);
155 tmp_r |= HW_POWER_DCDC4P2_ENABLE_4P2;
156 REG_WR(PWR_DCDC4P2, tmp_r);
168 tmp_r = REG_RD(PWR_DCDC4P2);
169 tmp_r |= HW_POWER_DCDC4P2_ENABLE_DCDC;
170 REG_WR(PWR_DCDC4P2, tmp_r);
175 tmp_r = REG_RD(PWR_5VCTRL);
177 tmp_r &= ~HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT;
178 tmp_r |= __SHIFTIN(ilimit, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT);
179 REG_WR(PWR_5VCTRL, tmp_r);
191 uint32_t tmp_r;
193 tmp_r = REG_RD(PWR_DCDC4P2);
195 tmp_r &= ~HW_POWER_DCDC4P2_CMPTRIP;
196 tmp_r |= __SHIFTIN(CMPTRIP, HW_POWER_DCDC4P2_CMPTRIP);
198 tmp_r &= ~HW_POWER_DCDC4P2_DROPOUT_CTRL;
199 tmp_r |= __SHIFTIN(DROPOUT_CTRL, HW_POWER_DCDC4P2_DROPOUT_CTRL);
201 REG_WR(PWR_DCDC4P2, tmp_r);
223 uint32_t tmp_r;
233 tmp_r = REG_RD(PWR_VDDDCTRL);
234 tmp_r &= ~HW_POWER_VDDDCTRL_LINREG_OFFSET;
235 tmp_r |= __SHIFTIN(2, HW_POWER_VDDDCTRL_LINREG_OFFSET);
236 REG_WR(PWR_VDDDCTRL, tmp_r);
240 tmp_r = REG_RD(PWR_VDDDCTRL);
241 tmp_r &= ~HW_POWER_VDDDCTRL_DISABLE_FET;
242 REG_WR(PWR_VDDDCTRL, tmp_r);
246 tmp_r = REG_RD(PWR_VDDDCTRL);
247 tmp_r &= ~HW_POWER_VDDDCTRL_ENABLE_LINREG;
248 REG_WR(PWR_VDDDCTRL, tmp_r);
252 tmp_r = REG_RD(PWR_VDDDCTRL);
253 tmp_r &= ~(HW_POWER_VDDDCTRL_BO_OFFSET | HW_POWER_VDDDCTRL_TRG);
254 tmp_r |= __SHIFTIN(((target - brownout) / 25),
256 tmp_r |= __SHIFTIN(((target - 800) / 25), HW_POWER_VDDDCTRL_TRG);
257 REG_WR(PWR_VDDDCTRL, tmp_r);
263 tmp_r = REG_RD(PWR_VDDDCTRL);
264 tmp_r |= HW_POWER_VDDDCTRL_PWDN_BRNOUT;
265 REG_WR(PWR_VDDDCTRL, tmp_r);
275 uint32_t tmp_r;
285 tmp_r = REG_RD(PWR_VDDACTRL);
286 tmp_r &= ~HW_POWER_VDDACTRL_LINREG_OFFSET;
287 tmp_r |= __SHIFTIN(2, HW_POWER_VDDACTRL_LINREG_OFFSET);
288 REG_WR(PWR_VDDACTRL, tmp_r);
292 tmp_r = REG_RD(PWR_VDDACTRL);
293 tmp_r &= ~HW_POWER_VDDACTRL_DISABLE_FET;
294 REG_WR(PWR_VDDACTRL, tmp_r);
298 tmp_r = REG_RD(PWR_VDDACTRL);
299 tmp_r &= ~HW_POWER_VDDACTRL_ENABLE_LINREG;
300 REG_WR(PWR_VDDACTRL, tmp_r);
304 tmp_r = REG_RD(PWR_VDDACTRL);
305 tmp_r &= ~(HW_POWER_VDDACTRL_BO_OFFSET | HW_POWER_VDDACTRL_TRG);
306 tmp_r |= __SHIFTIN(((target - brownout) / 25),
308 tmp_r |= __SHIFTIN(((target - 1500) / 25), HW_POWER_VDDACTRL_TRG);
309 REG_WR(PWR_VDDACTRL, tmp_r);
315 tmp_r = REG_RD(PWR_VDDACTRL);
316 tmp_r |= HW_POWER_VDDACTRL_PWDN_BRNOUT;
317 REG_WR(PWR_VDDACTRL, tmp_r);
327 uint32_t tmp_r;
337 tmp_r = REG_RD(PWR_VDDIOCTRL);
338 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET;
339 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET);
340 REG_WR(PWR_VDDIOCTRL, tmp_r);
344 tmp_r = REG_RD(PWR_VDDIOCTRL);
345 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
346 REG_WR(PWR_VDDIOCTRL, tmp_r);
350 tmp_r = REG_RD(PWR_VDDIOCTRL);
351 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG);
352 tmp_r |= __SHIFTIN(((target - brownout) / 25),
354 tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG);
355 REG_WR(PWR_VDDIOCTRL, tmp_r);
361 tmp_r = REG_RD(PWR_VDDIOCTRL);
362 tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT;
363 REG_WR(PWR_VDDIOCTRL, tmp_r);
373 uint32_t tmp_r;
376 tmp_r = REG_RD(PWR_VDDMEMCTRL);
377 tmp_r &= ~(HW_POWER_VDDMEMCTRL_TRG);
378 tmp_r |= __SHIFTIN(((target - 1700) / 50), HW_POWER_VDDMEMCTRL_TRG);
379 REG_WR(PWR_VDDMEMCTRL, tmp_r);
382 tmp_r = REG_RD(PWR_VDDMEMCTRL);
383 tmp_r |= (HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
386 REG_WR(PWR_VDDMEMCTRL, tmp_r);
390 tmp_r = REG_RD(PWR_VDDMEMCTRL);
391 tmp_r &= ~(HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE |
393 REG_WR(PWR_VDDMEMCTRL, tmp_r);
Indexes created Tue Sep 30 20:09:53 GMT 2025