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Lines Matching refs:writereg

78 	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
79 	writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
97 	writereg(JZ_TC_TMCR, TFR_OSTFLAG);
99 	writereg(JZ_TC_TECR, TESR_TCST5);	/* disable timer 5 */
100 	writereg(JZ_TC_TCNT(5), 0);
101 	writereg(JZ_TC_TDFR(5), 30000);	/* 10ms at 48MHz / 16 */
102 	writereg(JZ_TC_TDHR(5), 60000);	/* not reached */
103 	writereg(JZ_TC_TCSR(5), TCSR_EXT_EN| TCSR_DIV_16);
104 	writereg(JZ_TC_TMCR, TFR_FFLAG5);
105 	writereg(JZ_TC_TFCR, TFR_FFLAG5);
106 	writereg(JZ_TC_TESR, TESR_TCST5);	/* enable timer 5 */
113 	writereg(JZ_ICMCR0, 0x0c000000); /* TCU2, OST */
203 	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
207 	writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
219 		writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
222 	writereg(JZ_TC_TFCR, TFR_OSTFLAG);
224 	writereg(JZ_TC_TFCR, TFR_FFLAG5);