Lines Matching refs:data
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
216 pcireg_t data;
231 data = 0;
235 data = glx_fn0_read(offset);
240 data = glx_fn2_read(offset);
243 data = glx_fn3_read(offset);
246 data = glx_fn4_read(offset);
249 data = glx_fn5_read(offset);
257 return data;
262 int offset, pcireg_t data)
273 gen_pci_conf_write(v, tag, offset, data);
280 gen_pci_conf_write(v, tag, offset, data);
286 glx_fn0_write(offset, data);
291 glx_fn2_write(offset, data);
294 glx_fn3_write(offset, data);
297 glx_fn4_write(offset, data);
300 glx_fn5_write(offset, data);
313 pcireg_t data;
315 data = 0;
318 data |= PCI_COMMAND_PARITY_ENABLE;
319 data |= PCI_STATUS_66MHZ_SUPPORT |
322 data |= PCI_STATUS_PARITY_DETECT;
324 data |= PCI_STATUS_TARGET_TARGET_ABORT;
326 data |= PCI_STATUS_MASTER_TARGET_ABORT;
328 data |= PCI_STATUS_MASTER_ABORT;
330 return data;
361 pcireg_t data;
367 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_PCIB);
370 data = glx_get_status();
371 data |= PCI_COMMAND_MASTER_ENABLE;
374 data |= PCI_COMMAND_IO_ENABLE;
378 data = (PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) |
384 data = (0x80 << PCI_HDRTYPE_SHIFT) |
397 data = 0;
399 data = pcib_bar_values[index];
400 if (data == 0xffffffff)
401 data = PCI_MAPREG_IO_ADDR_MASK;
403 data = (pcireg_t)rdmsr(pcib_bar_msr[index]);
404 data &= ~(pcib_bar_sizes[index] - 1);
405 if (data != 0)
406 data |= PCI_MAPREG_TYPE_IO;
410 data = (0x40 << PCI_MAX_LAT_SHIFT) |
414 data = 0;
418 return data;
422 glx_fn0_write(int reg, pcireg_t data)
433 if (data & PCI_COMMAND_IO_ENABLE)
441 if (data & PCI_COMMAND_PARITY_ENABLE)
450 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
460 if (data == 0xffffffff) {
461 pcib_bar_values[index] = data;
463 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) {
464 data &= PCI_MAPREG_IO_ADDR_MASK;
465 data &= ~(pcib_bar_sizes[index] - 1);
467 (0x0000f000ULL << 32) | (1ULL << 32) | data);
488 pcireg_t data;
493 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_IDE);
496 data = glx_get_status();
497 data |= PCI_COMMAND_IO_ENABLE;
500 data |= PCI_COMMAND_MASTER_ENABLE;
504 data = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) |
511 data = (0x00 << PCI_HDRTYPE_SHIFT) |
516 data = pciide_bar_value;
517 if (data == 0xffffffff)
518 data = PCI_MAPREG_IO_ADDR_MASK & ~(pciide_bar_size - 1);
521 data = msr & 0xfffffff0;
523 if (data != 0)
524 data |= PCI_MAPREG_TYPE_IO;
528 data = (0x40 << PCI_MAX_LAT_SHIFT) |
535 data = rdmsr(GCSC_IDE_CFG);
538 data = rdmsr(GCSC_IDE_DTC);
541 data = rdmsr(GCSC_IDE_ETC);
545 data = 0;
549 return data;
553 glx_fn2_write(int reg, pcireg_t data)
560 if (data & PCI_COMMAND_MASTER_ENABLE)
569 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
572 if (data == 0xffffffff) {
573 pciide_bar_value = data;
575 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) {
576 data &= PCI_MAPREG_IO_ADDR_MASK;
577 msr = (uint32_t)data & 0xfffffff0;
589 wrmsr(GCSC_IDE_CFG, (uint32_t)data);
592 wrmsr(GCSC_IDE_DTC, (uint32_t)data);
595 wrmsr(GCSC_IDE_ETC, (uint32_t)data);
613 pcireg_t data;
618 data = PCI_ID_CODE(PCI_VENDOR_AMD,
622 data = glx_get_status();
623 data |= PCI_COMMAND_IO_ENABLE;
626 data |= PCI_COMMAND_MASTER_ENABLE;
630 data = (PCI_CLASS_MULTIMEDIA << PCI_CLASS_SHIFT) |
636 data = (0x00 << PCI_HDRTYPE_SHIFT) |
641 data = ac97_bar_value;
642 if (data == 0xffffffff)
643 data = PCI_MAPREG_IO_ADDR_MASK & ~(ac97_bar_size - 1);
646 data = (msr >> 20) & 0x000fffff;
647 data &= (msr & 0x000fffff);
649 if (data != 0)
650 data |= PCI_MAPREG_TYPE_IO;
653 data = (0x40 << PCI_MAX_LAT_SHIFT) |
657 data = 0;
661 return data;
665 glx_fn3_write(int reg, pcireg_t data)
672 if (data & PCI_COMMAND_MASTER_ENABLE)
681 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
684 if (data == 0xffffffff) {
685 ac97_bar_value = data;
687 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) {
688 data &= PCI_MAPREG_IO_ADDR_MASK;
692 msr |= ((uint64_t)data & 0xfffff) << 20;
715 pcireg_t data;
720 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_OHCI);
723 data = glx_get_status();
726 data |= PCI_COMMAND_MASTER_ENABLE;
728 data |= PCI_COMMAND_MEM_ENABLE;
732 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) |
739 data = (0x00 << PCI_HDRTYPE_SHIFT) |
744 data = ohci_bar_value;
745 if (data == 0xffffffff)
746 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ohci_bar_size - 1);
749 data = msr & 0xffffff00;
751 if (data != 0)
752 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT;
755 data = 0x40;
758 data = (0x40 << PCI_MAX_LAT_SHIFT) |
762 data = 0;
765 data = 0;
769 return data;
773 glx_fn4_write(int reg, pcireg_t data)
780 if (data & PCI_COMMAND_MASTER_ENABLE)
784 if (data & PCI_COMMAND_MEM_ENABLE)
793 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
796 if (data == 0xffffffff) {
797 ohci_bar_value = data;
799 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_MEM) {
800 data &= PCI_MAPREG_MEM_ADDR_MASK;
804 msr |= (((uint64_t)data) >> 12) << 20;
810 msr |= data;
835 pcireg_t data;
840 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_EHCI);
843 data = glx_get_status();
846 data |= PCI_COMMAND_MASTER_ENABLE;
848 data |= PCI_COMMAND_MEM_ENABLE;
852 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) |
859 data = (0x00 << PCI_HDRTYPE_SHIFT) |
864 data = ehci_bar_value;
865 if (data == 0xffffffff)
866 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ehci_bar_size - 1);
869 data = msr & 0xffffff00;
871 if (data != 0)
872 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT;
875 data = 0x40;
878 data = (0x40 << PCI_MAX_LAT_SHIFT) |
882 data = 0;
886 data = PCI_USBREV_2_0;
887 data |= ((msr >> 40) & 0x3f) << 8; /* PCI_EHCI_FLADJ */
890 data = 0;
894 return data;
898 glx_fn5_write(int reg, pcireg_t data)
905 if (data & PCI_COMMAND_MASTER_ENABLE)
909 if (data & PCI_COMMAND_MEM_ENABLE)
918 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
921 if (data == 0xffffffff) {
922 ehci_bar_value = data;
924 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_MEM) {
925 data = PCI_MAPREG_MEM_ADDR(data);
929 msr |= (((uint64_t)data) >> 12) << 20;
935 msr |= data;
Indexes created Wed Oct 15 07:09:58 GMT 2025