Lines Matching refs:msr
67 /* MSR access through PCI configuration space */
73 /* access to the MSR through the PCI mailbox needs the same transformation
74 * as done by hardware when a MSR request reaches the CS5536.
82 glx_msra2mbxa(uint msr)
84 uint rf = (msr & GLX_MSR_ADDR_RF);
85 return ((rf << GLX_MSR_ADDR_RF_SHIFT) | (msr & GLX_MSR_ADDR_TARGET));
113 uint64_t msr;
133 msr = rdmsr(GCSC_DIVIL_BALL_OPTS); /* 0x71 */
134 wrmsr(GCSC_DIVIL_BALL_OPTS, msr | 0x01);
139 msr = 0;
140 msr |= 11 << 8;
141 msr |= 9 << 16;
142 wrmsr(GCSC_PIC_YSEL_LOW, msr);
147 msr = 0;
148 msr |= 4 << 24;
149 msr |= 3 << 28;
150 wrmsr(GCSC_PIC_YSEL_HIGH, msr);
155 msr = 0;
156 msr |= 1 << 14;
157 wrmsr(GCSC_PIC_IRQM_PRIM, msr);
162 msr = 0;
163 msr |= 1 << 1; /* keyboard */
164 msr |= 1 << 12; /* mouse */
165 wrmsr(GCSC_PIC_IRQM_LPC, msr);
175 rdmsr(uint msr)
187 glx_msra2mbxa(msr));
195 wrmsr(uint msr, uint64_t value)
206 glx_msra2mbxa(msr));
222 * Do not get in the way of MSR programming
270 * Do not get in the way of MSR programming
312 uint64_t msr;
316 msr = rdmsr(GCSC_GLPCI_GLD_MSR_ERROR);
317 if (msr & (1UL << 5))
321 if (msr & (1UL << 21))
323 if (msr & (1UL << 20))
325 if (msr & (1UL << 17))
327 if (msr & (1UL << 16))
360 uint64_t msr;
372 msr = rdmsr(GCSC_DIVIL_LBAR_SMB);
373 if (msr & (1ULL << 32))
377 msr = rdmsr(GCSC_GLCP_CHIP_REV_ID);
380 (msr & PCI_REVISION_MASK);
383 msr = rdmsr(GCSC_GLPCI_CTRL);
385 (((msr & 0xff00000000UL) >> 32) << PCI_LATTIMER_SHIFT) |
424 uint64_t msr;
432 msr = rdmsr(pcib_bar_msr[index]);
434 msr |= 1ULL << 32;
436 msr &= ~(1ULL << 32);
437 wrmsr(pcib_bar_msr[index], msr);
440 msr = rdmsr(GCSC_GLPCI_GLD_MSR_ERROR);
442 msr |= 1ULL << 5;
444 msr &= ~(1ULL << 5);
445 wrmsr(GCSC_GLPCI_GLD_MSR_ERROR, msr);
448 msr = rdmsr(GCSC_GLPCI_CTRL);
449 msr &= 0xff00000000ULL;
450 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
487 uint64_t msr;
498 msr = rdmsr(GCSC_GLIU_PAE);
499 if ((msr & (0x3 << 4)) == (0x3 << 4))
503 msr = rdmsr(GCSC_IDE_GLD_MSR_CAP);
507 (msr & PCI_REVISION_MASK);
510 msr = rdmsr(GCSC_GLPCI_CTRL);
512 (((msr & 0xff00000000ULL) >> 32) << PCI_LATTIMER_SHIFT) |
520 msr = rdmsr(GCSC_IDE_IO_BAR);
521 data = msr & 0xfffffff0;
555 uint64_t msr;
559 msr = rdmsr(GCSC_GLIU_PAE);
561 msr |= 0x03 << 4;
563 msr &= ~(0x03 << 4);
564 wrmsr(GCSC_GLIU_PAE, msr);
567 msr = rdmsr(GCSC_GLPCI_CTRL);
568 msr &= 0xff00000000ULL;
569 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
577 msr = (uint32_t)data & 0xfffffff0;
578 wrmsr(GCSC_IDE_IO_BAR, msr);
612 uint64_t msr;
624 msr = rdmsr(GCSC_GLIU_PAE);
625 if ((msr & (0x3 << 8)) == (0x3 << 8))
629 msr = rdmsr(GCSC_ACC_GLD_MSR_CAP);
632 (msr & PCI_REVISION_MASK);
635 msr = rdmsr(GCSC_GLPCI_CTRL);
637 (((msr & 0xff00000000ULL) >> 32) << PCI_LATTIMER_SHIFT) |
645 msr = rdmsr(GCSC_GLIU_IOD_BM1);
646 data = (msr >> 20) & 0x000fffff;
647 data &= (msr & 0x000fffff);
667 uint64_t msr;
671 msr = rdmsr(GCSC_GLIU_PAE);
673 msr |= 0x03 << 8;
675 msr &= ~(0x03 << 8);
676 wrmsr(GCSC_GLIU_PAE, msr);
679 msr = rdmsr(GCSC_GLPCI_CTRL);
680 msr &= 0xff00000000ULL;
681 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
689 msr = rdmsr(GCSC_GLIU_IOD_BM1);
690 msr &= 0x0fffff0000000000ULL;
691 msr |= 5ULL << 61; /* AC97 */
692 msr |= ((uint64_t)data & 0xfffff) << 20;
693 msr |= 0x000fffff & ~(ac97_bar_size - 1);
694 msr);
714 uint64_t msr;
724 msr = rdmsr(GCSC_USB_MSR_OHCB);
725 if (msr & (1ULL << 34))
727 if (msr & (1ULL << 33))
731 msr = rdmsr(GCSC_USB_GLD_MSR_CAP);
735 (msr & PCI_REVISION_MASK);
738 msr = rdmsr(GCSC_GLPCI_CTRL);
740 (((msr & 0xff00000000ULL) >> 32) << PCI_LATTIMER_SHIFT) |
748 msr = rdmsr(GCSC_USB_MSR_OHCB);
749 data = msr & 0xffffff00;
775 uint64_t msr;
779 msr = rdmsr(GCSC_USB_MSR_OHCB);
781 msr |= 1ULL << 34;
783 msr &= ~(1ULL << 34);
785 msr |= 1ULL << 33;
787 msr &= ~(1ULL << 33);
788 wrmsr(GCSC_USB_MSR_OHCB, msr);
791 msr = rdmsr(GCSC_GLPCI_CTRL);
792 msr &= 0xff00000000ULL;
793 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
801 msr = rdmsr(GCSC_GLIU_P2D_BM3);
802 msr &= 0x0fffff0000000000ULL;
803 msr |= 2ULL << 61; /* USB */
804 msr |= (((uint64_t)data) >> 12) << 20;
805 msr |= 0x000fffff;
806 wrmsr(GCSC_GLIU_P2D_BM3, msr);
808 msr = rdmsr(GCSC_USB_MSR_OHCB);
809 msr &= ~0xffffff00ULL;
810 msr |= data;
812 msr = rdmsr(GCSC_USB_MSR_OHCB);
813 msr &= ~0xffffff00ULL;
815 wrmsr(GCSC_USB_MSR_OHCB, msr);
834 uint64_t msr;
844 msr = rdmsr(GCSC_USB_MSR_EHCB);
845 if (msr & (1ULL << 34))
847 if (msr & (1ULL << 33))
851 msr = rdmsr(GCSC_USB_GLD_MSR_CAP);
855 (msr & PCI_REVISION_MASK);
858 msr = rdmsr(GCSC_GLPCI_CTRL);
860 (((msr & 0xff00000000ULL) >> 32) << PCI_LATTIMER_SHIFT) |
868 msr = rdmsr(GCSC_USB_MSR_EHCB);
869 data = msr & 0xffffff00;
885 msr = rdmsr(GCSC_USB_MSR_EHCB);
887 data |= ((msr >> 40) & 0x3f) << 8; /* PCI_EHCI_FLADJ */
900 uint64_t msr;
904 msr = rdmsr(GCSC_USB_MSR_EHCB);
906 msr |= 1ULL << 34;
908 msr &= ~(1ULL << 34);
910 msr |= 1ULL << 33;
912 msr &= ~(1ULL << 33);
913 wrmsr(GCSC_USB_MSR_EHCB, msr);
916 msr = rdmsr(GCSC_GLPCI_CTRL);
917 msr &= 0xff00000000ULL;
918 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32;
926 msr = rdmsr(GCSC_GLIU_P2D_BM4);
927 msr &= 0x0fffff0000000000ULL;
928 msr |= 2ULL << 61; /* USB */
929 msr |= (((uint64_t)data) >> 12) << 20;
930 msr |= 0x000fffff;
931 wrmsr(GCSC_GLIU_P2D_BM4, msr);
933 msr = rdmsr(GCSC_USB_MSR_EHCB);
934 msr &= ~0xffffff00ULL;
935 msr |= data;
937 msr = rdmsr(GCSC_USB_MSR_EHCB);
938 msr &= ~0xffffff00ULL;
940 wrmsr(GCSC_USB_MSR_EHCB, msr);
Indexes created Wed Oct 22 13:09:56 GMT 2025