Cross Reference: /src/sys/arch/evbppc/nintendo/dev/ahb.c

Lines Matching refs:irq
169 		aprint_normal(" irq %d", aaa->aaa_irq);
176 hollywood_enable_irq(struct pic_ops *pic, int irq, int type)
178 	pic_irqmask[0] |= __BIT(irq);
183 hollywood_disable_irq(struct pic_ops *pic, int irq)
185 	pic_irqmask[0] &= ~__BIT(irq);
193 	int irq;
200 	irq = ffs32(pend) - 1;
202 	return irq;
206 hollywood_ack_irq(struct pic_ops *pic, int irq)
208 	WR4(HW_PPCIRQFLAGS, __BIT(irq));
212 hollywood_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
218 	val &= ~__BIT(irq);
220 	WR4(HW_ARMIRQFLAGS, __BIT(irq));
224 latte_enable_irq(struct pic_ops *pic, int irq, int type)
226 	unsigned reg_en = irq < 32 ? LT_PPCnINT1EN(0) : LT_PPCnINT2EN(0);
228 	pic_irqmask[irq / 32] |= __BIT(irq % 32);
229 	WR4(reg_en, pic_irqmask[irq / 32]);
233 latte_disable_irq(struct pic_ops *pic, int irq)
235 	unsigned reg_en = irq < 32 ? LT_PPCnINT1EN(0) : LT_PPCnINT2EN(0);
237 	pic_irqmask[irq / 32] &= ~__BIT(irq % 32);
238 	WR4(reg_en, pic_irqmask[irq / 32]);
245 	int irq;
255 		irq = 32 + ffs32(pend) - 1;
257 		irq = ffs32(pend) - 1;
260 	return irq;
264 latte_ack_irq(struct pic_ops *pic, int irq)
266 	unsigned reg_sts = irq < 32 ? LT_PPCnINT1STS(0) : LT_PPCnINT2STS(0);
268 	WR4(reg_sts, __BIT(irq % 32));
272 latte_establish_irq(struct pic_ops *pic, int irq, int type, int pri)
274 	unsigned reg_en = irq < 32 ? LT_IOPIRQINT1EN : LT_IOPIRQINT2EN;
275 	unsigned reg_sts = irq < 32 ? LT_IOPINT1STS : LT_IOPINT2STS;
280 	val &= ~__BIT(irq % 32);
282 	WR4(reg_sts, __BIT(irq % 32));
287 ahb_intr_init(int irq)
308 	intr_establish_xname(irq, IST_LEVEL, IPL_SCHED, pic_handle_intr,
313 ahb_intr_establish(int irq, int ipl, int (*func)(void *), void *arg,
319 		return intr_establish_xname(latte_pic.pic_intrbase + irq,
324 		return intr_establish_xname(hollywood_pic.pic_intrbase + irq,