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Lines Matching defs:zs

40 struct zs zs;
53 	zs.csr  = (volatile uint8_t *)csr;
54 	zs.data = (volatile uint8_t *)data;
55 	zs.clock = clock;
63 #define	ZS_WRITE_REG(zs, reg, val)	\
65 		*zs.csr = reg;		\
66 		*zs.csr = val;		\
73 	ZS_WRITE_REG(zs,  9, 0);
74 	ZS_WRITE_REG(zs,  9, ZSWR9_HARD_RESET);
76 	ZS_WRITE_REG(zs,  4, ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP);
77 	ZS_WRITE_REG(zs, 10, 0x00);
78 	ZS_WRITE_REG(zs,  3, ZSWR3_RX_8);
79 	ZS_WRITE_REG(zs,  5, ZSWR5_TX_8 | ZSWR5_DTR | ZSWR5_RTS);
81 	ZS_WRITE_REG(zs,  6, 0x00);
82 	ZS_WRITE_REG(zs,  7, 0x00);
84 	ZS_WRITE_REG(zs, 14, ZSWR14_BAUD_FROM_PCLK);
85 	ZS_WRITE_REG(zs, 11, ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD);
86 	ZS_WRITE_REG(zs, 12, BPS_TO_TCONST(zs.clock / 16, ZS_CONSDEFSPEED));
87 	ZS_WRITE_REG(zs, 13, 0);
89 	ZS_WRITE_REG(zs, 14, ZSWR14_BAUD_FROM_PCLK | ZSWR14_BAUD_ENA);
90 	ZS_WRITE_REG(zs, 15, 0x00);
92 	*zs.csr = ZSWR0_RESET_STATUS;
93 	*zs.csr = ZSWR0_RESET_STATUS;
95 	ZS_WRITE_REG(zs,  3, ZSWR3_RX_8 | ZSWR3_RX_ENABLE);
96 	ZS_WRITE_REG(zs,  5,
106 		csr = *zs.csr;
109 	data = *zs.data;
119 	csr = *zs.csr;
123 	data = *zs.data;
134 		csr = *zs.csr;
137 	*zs.data = c;