Lines Matching defs:hd
92 #define FHPIBWAIT(hd, m) while (((hd)->hpib_intr & (m)) == 0) DELAY(1)
196 struct fhpibdevice *hd = sc->sc_regs;
198 hd->hpib_cid = 0xFF;
200 hd->hpib_cmd = CT_8BIT;
201 hd->hpib_ar = AR_ARONC;
202 fhpibifc(hd);
203 hd->hpib_ie = IDS_IE;
204 hd->hpib_data = C_DCL;
210 hd->hpib_ie |= IDS_WDMA;
211 if (hd->hpib_ie & IDS_WDMA) {
212 hd->hpib_ie &= ~IDS_WDMA;
223 fhpibifc(struct fhpibdevice *hd)
226 hd->hpib_cmd |= CT_IFC;
227 hd->hpib_cmd |= CT_INITFIFO;
229 hd->hpib_cmd &= ~CT_IFC;
230 hd->hpib_cmd |= CT_REN;
231 hd->hpib_stat = ST_ATN;
238 struct fhpibdevice *hd = sc->sc_regs;
243 hd->hpib_stat = 0;
244 hd->hpib_imask = IM_IDLE | IM_ROOM;
245 if (fhpibwait(hd, IM_IDLE) < 0)
247 hd->hpib_stat = ST_ATN;
248 hd->hpib_data = C_UNL;
249 hd->hpib_data = C_TAG + hs->sc_ba;
250 hd->hpib_data = C_LAG + slave;
253 hd->hpib_data = C_SDC;
255 hd->hpib_data = C_SCG + sec;
256 if (fhpibwait(hd, IM_IDLE) < 0)
259 hd->hpib_stat = ST_WRITE;
261 hd->hpib_data = *addr++;
263 while ((hd->hpib_intr & IM_ROOM) == 0) {
269 hd->hpib_stat = ST_EOI;
270 hd->hpib_data = *addr;
271 FHPIBWAIT(hd, IM_ROOM);
272 hd->hpib_stat = ST_ATN;
276 hd->hpib_data = C_UNL;
277 (void) fhpibwait(hd, IM_IDLE);
279 hd->hpib_imask = 0;
283 hd->hpib_imask = 0;
284 fhpibifc(hd);
299 struct fhpibdevice *hd = sc->sc_regs;
309 hd->hpib_stat = 0;
310 hd->hpib_imask = IM_IDLE | IM_ROOM | IM_BYTE;
311 if (fhpibwait(hd, IM_IDLE) < 0)
313 hd->hpib_stat = ST_ATN;
314 hd->hpib_data = C_UNL;
315 hd->hpib_data = C_LAG + hs->sc_ba;
316 hd->hpib_data = C_TAG + slave;
318 hd->hpib_data = C_SCG + sec;
319 if (fhpibwait(hd, IM_IDLE) < 0)
321 hd->hpib_stat = ST_READ0;
322 hd->hpib_data = 0;
327 while ((hd->hpib_intr & IM_BYTE) == 0) {
332 *addr++ = hd->hpib_data;
334 FHPIBWAIT(hd, IM_ROOM);
335 hd->hpib_stat = ST_ATN;
336 hd->hpib_data = (slave == 31) ? C_UNA : C_UNT;
337 (void) fhpibwait(hd, IM_IDLE);
339 hd->hpib_imask = 0;
343 fhpibifc(hd);
345 hd->hpib_imask = 0;
361 struct fhpibdevice *hd = sc->sc_regs;
392 hd->hpib_latch = 0;
408 i = hd->hpib_cmd;
409 hd->hpib_cmd = sc->sc_cmd;
410 hd->hpib_ie = IDS_DMA(hs->sc_dq->dq_chan) |
436 i = hd->hpib_cmd;
437 hd->hpib_cmd = sc->sc_cmd;
438 hd->hpib_ie = IDS_DMA(hs->sc_dq->dq_chan) | IDS_WRITE |
457 struct fhpibdevice *hd = sc->sc_regs;
460 hd->hpib_imask = 0;
461 hd->hpib_cid = 0xFF;
463 hd->hpib_cmd = CT_8BIT;
464 hd->hpib_ar = AR_ARONC;
465 fhpibifc(hd);
466 hd->hpib_ie = IDS_IE;
480 struct fhpibdevice *hd = sc->sc_regs;
494 hd->hpib_imask = IM_IDLE | IM_BYTE;
502 hd->hpib_imask = IM_IDLE | IM_ROOM;
503 FHPIBWAIT(hd, IM_IDLE);
504 hd->hpib_stat = ST_WRITE;
506 hd->hpib_data = *addr++;
507 FHPIBWAIT(hd, IM_ROOM);
509 hd->hpib_stat = ST_EOI;
510 hd->hpib_data = *addr;
512 hd->hpib_imask = IM_IDLE;
515 hd->hpib_stat = ST_IENAB;
516 hd->hpib_ie = IDS_IE;
524 struct fhpibdevice *hd = sc->sc_regs;
528 stat0 = hd->hpib_ids;
554 stat0 = hd->hpib_cmd;
555 hd->hpib_cmd = sc->sc_cmd & ~CT_8BIT;
556 hd->hpib_stat = 0;
557 hd->hpib_cmd = CT_REN | CT_8BIT;
558 stat0 = hd->hpib_intr;
559 hd->hpib_imask = 0;
564 stat0 = hd->hpib_intr;
571 hd->hpib_stat = 0;
572 hd->hpib_imask = 0;
603 struct fhpibdevice *hd = sc->sc_regs;
606 hd->hpib_stat = 0;
607 hd->hpib_psense = 0;
608 hd->hpib_pmask = 0xFF;
609 hd->hpib_imask = IM_PPRESP | IM_PABORT;
611 hd->hpib_intr = IM_PABORT;
612 ppoll = hd->hpib_data;
613 if (hd->hpib_intr & IM_PABORT)
615 hd->hpib_imask = 0;
616 hd->hpib_pmask = 0;
617 hd->hpib_stat = ST_IENAB;
622 fhpibwait(struct fhpibdevice *hd, int x)
626 while ((hd->hpib_intr & x) == 0 && --timo)
631 printf("%s(%p, %x) timeout\n", __func__, hd, x);
647 struct fhpibdevice *hd = sc->sc_regs;
656 hd->hpib_stat = ST_IENAB;
657 hd->hpib_imask = IM_IDLE | IM_ROOM;
667 hd->hpib_psense = ~slave;
668 hd->hpib_pmask = slave;
669 hd->hpib_stat = ST_IENAB;
670 hd->hpib_imask = IM_PPRESP | IM_PABORT;
671 hd->hpib_ie = IDS_IE;
Indexes created Wed Oct 01 12:09:54 GMT 2025