Lines Matching defs:clock
72 { 640, 480, 25175, /* width, height, dot clock */
82 { 800, 600, 40000, /* width, height, dot clock */
90 { 1024, 768, 65000, /* width, height, dot clock */
150 mq200_set_pll(struct mq200_softc *sc, int pll, int clock)
175 if (clock != 0 && clock != -1) {
177 if (mq200_pllparam(clock, ¶m) != 0) {
178 printf("mq200: invalid clock rate: %s %d.%03dMHz\n",
179 mq200_clknames[pll], clock/1000, clock%1000);
188 mq200_clknames[pll], clock/1000, clock%1000);
219 const struct mq200_clock_setting *clock;
222 clock = &sc->sc_md->md_clock_settings[sc->sc_flags & MQ200_SC_GC_MASK];
236 * setup around clock
239 mq200_set_pll(sc, MQ200_CLOCK_PLL1, clock->pll1);
240 mq200_set_pll(sc, MQ200_CLOCK_PLL2, clock->pll2);
241 mq200_set_pll(sc, MQ200_CLOCK_PLL3, clock->pll3);
243 mq200_set_pll(sc, clock->gc[MQ200_GC1], crt->clock);
245 /* setup MEMORY clock */
246 if (clock->mem == MQ200_CLOCK_PLL2)
252 DPRINTF("MEM: PLL%d\n", (clock->mem == MQ200_CLOCK_PLL2)?2:1);
254 /* setup GE clock */
257 (clock->ge << MQ200_PMC_GE_CLK_SHIFT) | MQ200_PMC_GE_ENABLE);
258 DPRINTF(" GE: PLL%d\n", clock->ge);
288 (clock->gc[MQ200_GC1] << MQ200_GCC_RCLK_SHIFT) |
300 mq200_clknames[clock->gc[MQ200_GC1]]);
313 (clock->gc[MQ200_GC2] << MQ200_GCC_RCLK_SHIFT) |
316 mq200_clknames[clock->gc[MQ200_GC2]]);
325 if (clock->pll1 == 0) {
330 if (clock->pll2 == 0) {
335 if (clock->pll3 == 0) {