Lines Matching refs:cr
114 #define TX39_MEMCONFIG0_BANK1CONF(cr) \
115 (((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \
117 #define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \
118 ((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \
122 #define TX39_MEMCONFIG0_BANK0CONF(cr) \
123 (((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \
125 #define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \
126 ((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \
135 #define TX39_MEMCONFIG0_ROWSEL1(cr) \
136 (((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \
138 #define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \
139 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \
143 #define TX39_MEMCONFIG0_ROWSEL0(cr) \
144 (((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \
146 #define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \
147 ((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \
152 #define TX39_MEMCONFIG0_COLSEL1(cr) \
153 (((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \
155 #define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \
156 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \
160 #define TX39_MEMCONFIG0_COLSEL0(cr) \
161 (((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \
163 #define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \
164 ((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \
178 #define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \
179 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \
181 #define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \
182 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \
188 #define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \
189 (((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \
191 #define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \
192 ((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \
198 #define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \
199 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \
201 #define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \
202 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \
208 #define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \
209 (((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \
211 #define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \
212 ((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \
224 #define TX39_MEMCONFIG1_BCLKDIV(cr) \
225 (((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \
227 #define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \
228 ((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \
241 #define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \
242 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \
244 #define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \
245 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \
251 #define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \
252 (((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \
254 #define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \
255 ((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \
261 #define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \
262 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \
264 #define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \
265 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \
271 #define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \
272 (((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \
274 #define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \
275 ((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \
285 #define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \
286 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \
288 #define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \
289 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \
294 #define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \
295 (((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \
297 #define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \
298 ((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \
303 #define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \
304 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \
306 #define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \
307 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \
312 #define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \
313 (((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \
315 #define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \
316 ((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \
321 #define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \
322 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \
324 #define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \
325 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \
330 #define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \
331 (((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \
333 #define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \
334 ((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \
339 #define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \
340 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \
342 #define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \
343 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \
348 #define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \
349 (((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \
351 #define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \
352 ((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \
361 #define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \
362 (((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \
364 #define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \
365 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \
371 #define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \
372 (((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \
374 #define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \
375 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \
381 #define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \
382 (((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \
384 #define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \
385 ((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \
391 #define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \
392 (((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \
394 #define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \
395 ((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \
437 #define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \
438 (((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \
440 #define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \
441 ((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \
452 #define TX39_MEMCONFIG4_RFSHVAL1(cr) \
453 (((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \
455 #define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \
456 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \
461 #define TX39_MEMCONFIG4_RFSHVAL0(cr) \
462 (((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \
464 #define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \
465 ((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \
474 #define TX39_MEMCONFIG5_STARTVAL2(cr) \
475 (((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \
477 #define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \
478 ((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \
483 #define TX39_MEMCONFIG5_MASK2(cr) \
484 (((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \
486 #define TX39_MEMCONFIG5_MASK2_SET(cr, val) \
487 ((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \
496 #define TX39_MEMCONFIG6_STARTVAL1(cr) \
497 (((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \
499 #define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \
500 ((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \
505 #define TX39_MEMCONFIG6_MASK1(cr) \
506 (((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \
508 #define TX39_MEMCONFIG6_MASK1_SET(cr, val) \
509 ((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \
518 #define TX39_MEMCONFIG7_RMAPADD2(cr) \
519 (((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \
521 #define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \
522 ((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \
531 #define TX39_MEMCONFIG8_RMAPADD1(cr) \
532 (((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \
534 #define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \
535 ((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \
Indexes created Wed Oct 29 05:09:45 GMT 2025