Lines Matching refs:x3
54 #define BCUCNT1_ROMSMASK (0x3<<14) /* ROM SIZE (=4181) */
116 #define BCUCNT1_RTYPE (0x3<<1) /* ROM type (=4181) */
166 #define BCUROMSPEED_PATIME (0x3<<12) /* Page Access time */
167 #define BCUROMSPEED_PATIME_5VT (0x3<<12) /* 5VTClock */
185 #define BCUROMSPEED_ATIME_6VT (0x3) /* 6VTClock */
193 #define BCUIO0SPEED_RWCS (0x3<<12) /* R/W - CS time */
194 #define BCUIO0SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
212 #define BCUIO0SPEED_RDYRW_6VT (0x3) /* 6VTClock */
230 #define BCUIO0SPEED_RWRDY_2VT (0x3) /* 2VTClock */
248 #define BCUIO0SPEED_CSRW_4VT (0x3) /* 4VTClock */
256 #define BCUIO1SPEED_RWCS (0x3<<12) /* R/W - CS time */
257 #define BCUIO1SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
275 #define BCUIO1SPEED_RDYRW_6VT (0x3) /* 6VTClock */
293 #define BCUIO1SPEED_RWRDY_2VT (0x3) /* 2VTClock */
311 #define BCUIO1SPEED_CSRW_4VT (0x3) /* 4VTClock */
318 #define BCUSPD_WPROM (0x3<<12) /* Page ROM access speed */
319 #define BCUSPD_WPROMRFU (0x3<<12) /* RFU */
331 #define BCUSPD_WLCD2T (0x3<<8) /* LCD 2TClock */
340 #define BCUSPD_ISAM5T (0x3<<8) /* ISAM 5TClock */
348 #define BCUSPD_WISAA5T (0x3<<4) /* 5TClock */
358 #define BCUSPD_WROMA6T (0x3<<0) /* 6TClock */
377 #define BCU81SPD_WPROM4T (0x3<<12) /* 4TClock */
395 #define BCU81SPD_WROMA4T (0x3<<0) /* 4TClock */
412 #define BCUREVID_RID_4121 (0x3) /* VR4121 */
440 #define BCUCLKSPEED_DIVT3 0x3
453 #define BCU81CLKSPEED_DIVT2 0x3
461 #define BCUCLKSPEED_DIVVT3 0x3
473 #define BCUCLKSPEED_VTDIVT3 0x3
491 #define BCUCNT3_EXTROMCS (0x3<<12) /* Bank3,2 */
492 #define BCUCNT3_ROMROM (0x3<<12) /* Bank3 ROM ,2 ROM */
Indexes created Mon Oct 20 15:10:11 GMT 2025