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Lines Matching refs:setsioreg

189 		setsioreg(sc->sc_ctl, WR0, WR0_CHANRST);
190 		setsioreg(&siosc->sc_ctl[0], WR2A, WR2A_VEC86 | WR2A_INTR_1);
191 		setsioreg(&siosc->sc_ctl[1], WR2B, 0);
192 		setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
193 		setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
194 		setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);
195 		setsioreg(sc->sc_ctl, WR5, sc->sc_wr[WR5]);
196 		setsioreg(sc->sc_ctl, WR0, sc->sc_wr[WR0]);
198 	setsioreg(sc->sc_ctl, WR1, sc->sc_wr[WR1]); /* now interrupt driven */
452 	setsioreg(sc->sc_ctl, WR4, sc->sc_wr[WR4]);
453 	setsioreg(sc->sc_ctl, WR3, sc->sc_wr[WR3]);
454 	setsioreg(sc->sc_ctl, WR5, sc->sc_wr[WR5]);
500 	setsioreg(sc->sc_ctl, WR5, wr5);
718 	setsioreg(sio, WR0, WR0_CHANRST);
719 	setsioreg(sio_a, WR2A, WR2A_VEC86 | WR2A_INTR_1);
720 	setsioreg(sio_b, WR2B, 0);
721 	setsioreg(sio, WR0, ch0_regs[WR0]);
722 	setsioreg(sio, WR4, ch0_regs[WR4]);
723 	setsioreg(sio, WR3, ch0_regs[WR3]);
724 	setsioreg(sio, WR5, ch0_regs[WR5]);
725 	setsioreg(sio, WR0, ch0_regs[WR0]);