Lines Matching refs:VECTOR
111 VECTOR(buserr) /* 2: bus error */
112 VECTOR(addrerr) /* 3: address error */
113 VECTOR(illinst) /* 4: illegal instruction */
114 VECTOR(zerodiv) /* 5: zero divide */
115 VECTOR(chkinst) /* 6: CHK instruction */
116 VECTOR(trapvinst) /* 7: TRAPV instruction */
117 VECTOR(privinst) /* 8: privilege violation */
118 VECTOR(badtrap) /* 9: trace */
119 VECTOR(illinst) /* 10: line 1010 emulator */
120 VECTOR(illinst) /* 11: line 1111 emulator */
121 VECTOR(badtrap) /* 12: unassigned, reserved */
122 VECTOR(coperr) /* 13: coprocessor protocol violation */
123 VECTOR(fmterr) /* 14: format error */
124 VECTOR(badtrap) /* 15: uninitialized interrupt vector */
125 VECTOR(badtrap) /* 16: unassigned, reserved */
126 VECTOR(badtrap) /* 17: unassigned, reserved */
127 VECTOR(badtrap) /* 18: unassigned, reserved */
128 VECTOR(badtrap) /* 19: unassigned, reserved */
129 VECTOR(badtrap) /* 20: unassigned, reserved */
130 VECTOR(badtrap) /* 21: unassigned, reserved */
131 VECTOR(badtrap) /* 22: unassigned, reserved */
132 VECTOR(badtrap) /* 23: unassigned, reserved */
133 VECTOR(badtrap) /* 24: unassigned, reserved */
134 VECTOR(badtrap) /* 25: unassigned, reserved */
135 VECTOR(lev2intr) /* 26: level 2 interrupt autovector */
136 VECTOR(lev3intr) /* 27: level 3 interrupt autovector */
137 VECTOR(badtrap) /* 28: level 4 interrupt autovector */
138 VECTOR(lev5intr) /* 29: level 5 interrupt autovector */
139 VECTOR(lev6intr) /* 30: level 6 interrupt autovector */
140 VECTOR(exit) /* 31: level 7 interrupt autovector */
141 VECTOR(illinst) /* 32: syscalls */
142 VECTOR(illinst) /* 33: sigreturn syscall or breakpoint */
143 VECTOR(illinst) /* 34: breakpoint or sigreturn syscall */
144 VECTOR(illinst) /* 35: TRAP instruction vector */
145 VECTOR(illinst) /* 36: TRAP instruction vector */
146 VECTOR(illinst) /* 37: TRAP instruction vector */
147 VECTOR(illinst) /* 38: TRAP instruction vector */
148 VECTOR(illinst) /* 39: TRAP instruction vector */
149 VECTOR(illinst) /* 40: TRAP instruction vector */
150 VECTOR(illinst) /* 41: TRAP instruction vector */
151 VECTOR(illinst) /* 42: TRAP instruction vector */
152 VECTOR(illinst) /* 43: TRAP instruction vector */
153 VECTOR(illinst) /* 44: TRAP instruction vector */
154 VECTOR(illinst) /* 45: TRAP instruction vector */
155 VECTOR(illinst) /* 45: TRAP instruction vector */
156 VECTOR(illinst) /* 47: TRAP instruction vector */
157 VECTOR(fptrap) /* 48: FPCP branch/set on unordered cond */
158 VECTOR(fptrap) /* 49: FPCP inexact result */
159 VECTOR(fptrap) /* 50: FPCP divide by zero */
160 VECTOR(fptrap) /* 51: FPCP underflow */
161 VECTOR(fptrap) /* 52: FPCP operand error */
162 VECTOR(fptrap) /* 53: FPCP overflow */
163 VECTOR(fptrap) /* 54: FPCP signalling NAN */
165 VECTOR(badtrap) /* 55: unassigned, reserved */
166 VECTOR(badtrap) /* 56: unassigned, reserved */
167 VECTOR(badtrap) /* 57: unassigned, reserved */
168 VECTOR(badtrap) /* 58: unassigned, reserved */
169 VECTOR(badtrap) /* 59: unassigned, reserved */
170 VECTOR(badtrap) /* 60: unassigned, reserved */
171 VECTOR(badtrap) /* 61: unassigned, reserved */
172 VECTOR(badtrap) /* 62: unassigned, reserved */
173 VECTOR(badtrap) /* 63: unassigned, reserved */
175 VECTOR(badtrap) ; VECTOR(badtrap) ; \
176 VECTOR(badtrap) ; VECTOR(badtrap) ; \
177 VECTOR(badtrap) ; VECTOR(badtrap) ; \
178 VECTOR(badtrap) ; VECTOR(badtrap) ; \
179 VECTOR(badtrap) ; VECTOR(badtrap) ; \
180 VECTOR(badtrap) ; VECTOR(badtrap) ; \
181 VECTOR(badtrap) ; VECTOR(badtrap) ; \
182 VECTOR(badtrap) ; VECTOR(badtrap)
269 * Trap/interrupt vector routines
320 movw %a1@(8),%d0 | get frame format/vector offset
322 cmpw #12,%d0 | address error vector?
486 * Level 7: NMI: Abort Key (Dispatched vector to ROM monitor)
Indexes created Wed Oct 22 13:09:56 GMT 2025