Lines Matching refs:BITS
444 # FPSR/FPCR bits #
537 set mantissalen, 64 # length of mantissa in bits
1262 # I'm not sure at this point what FPSR bits are valid for this instruction.
1338 andi.b &0x38,%d0 # extract bits 3-5
1516 # I'm not sure at this point what FPSR bits are valid for this instruction.
1818 # I'm not sure at this point what FPSR bits are valid for this instruction.
1883 andi.b &0x38,%d0 # extract bits 3-5
2075 # I'm not sure at this point what FPSR bits are valid for this instruction.
3662 # bits four and five of the fp extension word separate the monadic and dyadic
4068 # bits 6-8 of the opword(classes 6,7 are undefined).
4095 andi.w &0x003f,%d1 # extract extension bits
4096 lsl.w &0x3,%d1 # shift right 3 bits
4097 or.b STAG(%a6),%d1 # insert src optag bits
4224 # force the fsave exception status bits to signal an exception of the
5029 # within 0.5001 ulp to 53 bits if the result is subsequently #
5734 # within 0.5001 ulp to 53 bits if the result is subsequently #
5798 #--MOST 69 BITS LONG.
6164 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
6174 # significant bits of X with a bit-1 attached at the 6-th #
6387 #--NOW WE SEE X AS +-2^K * 1.BBBBBBB....B <- 1. + 63 BITS
6389 #--THAT IS IT MATCHES THE EXPONENT AND FIRST 5 BITS OF X, THE
6390 #--SIXTH BITS IS SET TO BE 1. SINCE K = -4, -3, ..., 3, THERE
6396 and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS
6411 mov.l %d1,%d2 # THE EXP AND 16 BITS OF X
6412 and.l &0x00007800,%d1 # 4 VARYING BITS OF F'S FRACTION
6416 add.l %d2,%d1 # THE 7 BITS IDENTIFYING F
6614 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
6715 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
6811 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
6836 # 32-bit integer, the upper (more significant) 16 bits #
6838 # lower 16 bits are the 16 most significant fraction #
6839 # (including the explicit bit) bits of |X|. Consequently, #
6878 # approximate the value -log2/64 to 88 bits of accuracy. #
6879 # b) N*L1 is exact because N is no longer than 22 bits #
6880 # and L1 is no longer than 24 bits. #
6883 # 64 bits. #
6918 # 2^(J/64) to roughly 85 bits; T is in extended precision #
6920 # rounded to 62 bits so that the last two bits of T are #
7046 # 2^(J/64) to roughly 85 bits; T is in extended precision #
7048 # rounded to 62 bits so that the last two bits of T are #
7229 cmp.l %d1,&0x400CB167 # 16380 log2 trunc. 16 bits
7394 cmp.l %d1,&0x4004C215 # 70log2 rounded up to 16 bits
7692 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
7806 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
7924 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
8090 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
8101 # seven significant bits of Y plus 2**(-7), i.e. #
8355 #--WE DEFINE F = 1.XXXXXX1, I.E. FIRST 7 BITS OF Y AND ATTACH A 1.
8365 asr.l &8,%d1 # SHIFTED 16 BITS, BIASED EXPO. OF X
8374 and.l &0xFE000000,FFRAC(%a6) # FIRST 7 BITS OF Y
8499 #----normalize the input value by left shifting k bits (k to be determined
8581 #--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE,
8601 #--TAKEN BECAUSE 1+Z CAN HAVE 67 BITS OF INFORMATION AND WE MUST
8685 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
8775 # i.e. within 0.5003 ulp to 53 bits if the result is subsequently #
8939 # i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
9336 lsr.b &0x4,%d0 # shift ctrl bits to lo
9590 mov.l %d0,-(%sp) # store off ctrl bits for now
9609 # don't want any accrued bits from the fintrz showing up later since
9684 mov.l (%sp)+,%d0 # restore ctrl bits
9699 fmov.l %d0,%fpcr # no; load control bits
9704 mov.l (%sp)+,%d0 # load control bits into d1
9760 # Step 8. Return signQ, last 7 bits of Q, and R as required. #
9764 # R := 0. Return signQ, last 7 bits of Q, and R. #
9789 mov.l %d0,-(%sp) # save ctrl bits
9796 mov.l %d0,-(%sp) # save ctrl bits
10053 and.l &0x0000007F,%d3 # 7 bits of Q
10054 or.l %d6,%d3 # sign and bits of Q
10279 # the inexact bits if the number is inexact for the #
10315 mov.l LOCAL_LO(%a0),%d1 # are any of lo 11 bits of
10368 # - The inex2 and ainex bits are set. #
10429 lsr.b &0x4,%d0 # shift rnd prec,mode to lo bits
10436 mov.b (tbl_unf_cc.b,%pc,%d0.w*1),FPSR_CC(%a6) # insert ccode bits
10508 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits
10543 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
11414 # The location within the table is determined by the extension bits of the
11613 lsr.b &0x6,%d1 # shift to lo bits
11662 # set the inexact bits.
11746 # set the inexact bits.
11773 # set the inexact bits.
12436 lsr.b &0x6,%d1 # shift to lo bits
13196 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits
13209 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13229 # store the resulting FPSR bits. #
13256 or.l %d0,USER_FPSR(%a6) # set exception bits
13278 # also, the INEX2 and AINEX exception bits will be set.
13301 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13315 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
13335 # then store the resulting FPSR bits. #
13358 or.l %d0,USER_FPSR(%a6) # set exception bits
13380 # also, the INEX2 and AINEX exception bits will be set.
13403 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13417 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
13782 rol.l &0x8,%d0 # extract ccode bits
13783 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set)
14640 # the correct result exponent and return. Set FPSR bits as appropriate. #
14683 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
15093 # the correct result exponent and return. Set FPSR bits as appropriate. #
15136 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
15834 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
15869 # If the two exponents differ by > the number of mantissa bits #
16177 # Make sure the appropriate FPSR bits are set before exiting. #
16279 # bits are set in the stacked FPSR. If the BSUN exception is enabled, #
16908 # bits are set in the stacked FPSR. If the BSUN exception is enabled, #
17480 # bits are set in the stacked FPSR. If the BSUN exception is enabled, #
18229 andi.w &0x70,%d1 # extract reg bits
18230 lsr.b &0x4,%d1 # shift into lo bits
19009 btst &0x8,%d0 # is disp only 8 bits?
19246 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits
19639 btst &0x5,%d0 # testing extension bits
19643 and.w &0x007f,%d0 # extract extension bits {6:0}
19682 btst &0x5,%d0 # testing extension bits
19686 and.w &0x007f,%d0 # extract extension bits {6:0}
20244 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20290 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20336 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20892 bfextu %d1{&1:&20},%d1 # get upper 20 bits of ms
20893 or.l %d1,%d0 # put these bits in ms word of double
20897 lsl.l %d0,%d1 # put lower 11 bits in upper bits
20900 bfextu %d1{&0:&21},%d0 # get ls 21 bits of double
20951 lsl.l &0x7,%d0 # shift it into single exp bits
20957 andi.l &0x7fffff00,%d1 # get upper 23 bits of ms
20959 or.l %d1,%d0 # put these bits in ms word of single
21701 # precision, shift the mantissa bits to the right in order raise the #
21703 # mantissa bits right, maintain the value of the guard, round, and #
21704 # sticky bits. #
21727 lsr.b &0x2, %d0 # shift prec to lo bits
21731 cmpi.w %d0, &66 # is diff > 65? (mant + g,r bits)
21774 # make a copy of FTEMP_LO and place the g,r,s bits directly after it
21843 bftst %d0{&2:&30} # were bits shifted off?
21884 # the number of bits to check for the sticky detect.
21892 bftst %d1{&2:&30} # were any bits shifted off?
21894 bftst FTEMP_LO2(%a6){%d0:&31} # were any bits shifted off?
21928 # Shift value is > 65 and out of range. All bits are shifted off.
21960 and.l &0x3fffffff, %d1 # extract other bits
21988 and.l &0x7fffffff, %d1 # extract other bits
21991 # last operation done was an "and" of the bits shifted off so the condition
21994 tst.l FTEMP_LO(%a0) # were any bits shifted off?
21996 tst.b GRS(%a6) # were any bits shifted off?
22000 # no bits were shifted off so don't set the sticky bit.
22009 # some bits were shifted off so set the sticky bit.
22036 # d0{31:29} = contains the g,r,s bits (extended) #
22043 # a0 is preserved and the g-r-s bits in d0 are cleared. #
22048 # inexact (i.e. if any of the g-r-s bits were set). #
22056 # G,R,S bits.
22149 and.l &0xffffff00, FTEMP_HI(%a0) # truncate bits beyond sgl limit
22193 and.l &0xfffff800,FTEMP_LO(%a0) # truncate bits beyond dbl limit
22197 # Truncate all other bits #
22209 # ext_grs(): extract guard, round and sticky bits according to
22218 # The ext_grs extract the guard/round/sticky bits according to the
22261 bfextu FTEMP_HI(%a0){&24:&2}, %d3 # sgl prec. g-r are 2 bits right
22263 lsl.l %d2, %d3 # shift g-r bits to MSB of d3
22266 bne.b ext_grs_st_stky # bits to the right of g-r
22286 bfextu FTEMP_LO(%a0){&21:&2}, %d3 # dbl-prec. g-r are 2 bits right
22288 lsl.l %d2, %d3 # shift g-r bits to the MSB of d3
22291 bne.b ext_grs_st_stky # other bits to the right of g-r
22338 bfextu %d1{&0:%d2}, %d3 # extract lo bits
22394 # hi(man) is all zeroes so see if any bits in lo(man) are set
22447 # only mantissa bits set are in lo(man)
22697 # exponent is extended to 16 bits and the sign is stored in the unused #
22701 # Set the FPSR_exc bits as appropriate but return the cc bits in #
22851 # d0.b = condition code bits #
22855 # the result and the rounding mode/prec in effect. These bits are #
23289 mov.l &3,%d2 # init d2 to count bits in counter
23337 mov.l &3,%d2 # init d2 to count bits in counter
23393 bfextu %d3{&26:&2},%d2 # isolate rounding mode bits
23399 mov.b (%a1,%d2),%d0 # load new rounding bits from table
23401 bfins %d0,%d3{&26:&2} # stuff new rounding bits in FPCR
23477 # d0 = contains the k-factor sign-extended to 32-bits. #
23526 # only one rounding error. The grs bits are collected in #
23568 # A16. Write sign bits to final string. #
23602 # d2: upper 32-bits of mantissa for binstr
23603 # d3: scratch;lower 32-bits of mantissa for binstr
23857 bfextu USER_FPCR(%a6){&26:&2},%d1 # get initial rmode bits
23858 lsl.w &1,%d1 # put them in bits 2:1
23860 lsl.w &1,%d1 # put them in bits 3:1
23867 lsl.l &4,%d3 # put bits in proper position
23868 fmov.l %d3,%fpcr # load bits into fpu
23869 lsr.l &4,%d3 # put bits in proper position
23895 # only one rounding error. The grs bits are collected in
24081 fmov.l &0x0,%fpsr # clear the AEXC bits!!!
24224 # d2: x/ms 32-bits of mant of abs(YINT)
24225 # d3: x/ls 32-bits of mant of abs(YINT)
24297 # d2: x/ms 32-bits of exp fraction/scratch
24298 # d3: x/ls 32-bits of exp fraction
24371 # A16. Write sign bits to final string.
24409 fmov.l &0,%fpsr # clear possible inex2/ainex bits
24478 # shift and a mul by 8 shift. The bits shifted out of the #
24484 # to force the first byte formed to have a 0 in the upper 4 bits. #
24513 # d2: upper 32-bits of fraction for mul by 8
24514 # d3: lower 32-bits of fraction for mul by 8
24515 # d4: upper 32-bits of fraction for mul by 2
24516 # d5: lower 32-bits of fraction for mul by 2
24555 add.l %d5,%d3 # add lower 32 bits
24557 addx.l %d4,%d2 # add with extend upper 32 bits
24568 asl.w &4,%d7 # first digit in upper 4 bits d7b
24582 lsl.w &4,%d7 # move it to upper 4 bits
Indexes created Mon Oct 27 08:10:08 GMT 2025