Lines Matching refs:HAVE
731 # the exceptional possibilities we have left ourselves with are ONLY overflow
748 # overflow is enabled AND overflow, of course, occurred. so, we have the EXOP
979 # the exceptional possibilities we have left ourselves with are ONLY overflow
998 # overflow is enabled AND overflow, of course, occurred. so, we have the EXOP
1000 # well, we simply have to get to go to _real_unfl()!
1036 # then we have to branch to real_inex.
1251 # Separate opclass three (fpn-to-mem) ops since they have a different
1269 # Opclass two w/ memory-to-fpn operation will have an incorrect extended
1437 # "corrected" in order to have the proper equivalent extended precision
1570 # it here. if it was used from supervisor mode, then we have to handle this
1599 # for fp0/fp1 which have already been restored. that way, we can write
2307 # have to make sure that for single or double source operands that the
2493 # here, we will have:
2663 # enabled? if so, then we have to stuff an overflow frame into the FPU.
2672 # an enabled exception occurred. we have to insert the exception type back into
2680 # or underflow that was disabled, then we have to force an overflow or
2774 # the data has been fetched from the supervisor stack, but we have not
2953 # The FPU is disabled and so we should really have taken the "Line
2991 # modes and thus can have several different total instruction lengths.
4214 # or underflow that was disabled, then we have to force an overflow or
4217 # way to have the EXOP available for the enabled inexact handler when
4435 # as usual, we have to check for trace mode being on here. since instructions
5559 fmov.l %fpcr,%d0 # d0 must have fpcr,too
6428 #--THAT'S ALL I HAVE TO DO FOR NOW,
6435 #--WHAT WE HAVE HERE IS MERELY A1 = A3, A2 = A1/A3, A3 = A2/A3.
6650 # detected inside of satan(), the exception would have been handled there
6844 # |X| < 16380 log(2). There is no harm to have a small #
6932 # Notes: If AdjFlag = 0, we have X = Mlog2 + Jlog2/64 + R, #
8601 #--TAKEN BECAUSE 1+Z CAN HAVE 67 BITS OF INFORMATION AND WE MUST
8606 #--ON RETURNING TO LP1CONT1, WE MUST HAVE K IN FP1, ADDRESS OF
10073 # preceding fmul was a denorm. but, it better not have been since the
10169 # - For all functions that have a denormalized input and #
10217 # we have a DENORM that needs to be converted into an EXOP.
10294 # dst op is a DENORM. we have to normalize the mantissa to see if the
10352 # routine may have caused an underflow or overflow. #
11379 # ok, I have a problem with putting the dst op at FP_DST. the emulation
11558 # compute a result. Check if the regular operands would have taken #
11665 # extended precision. if the original operation was extended, then we have this
11666 # result. if the original operation was single or double, we have to do another
11704 # - if precision is extended, then we have the EXOP. simply bias the exponent
11766 # no, it didn't overflow; we have correct result
11776 # extended precision. if the original operation was extended, then we have this
11777 # result. if the original operation was single or double, we have to do another
11810 or.b %d0,FPSR_CC(%a6) # unf_res2 may have set 'Z'
11824 # if the rnd mode is anything but RZ, then we have to re-do the above
12053 # if the result would have overflowed/underflowed. If so, use unf_res() #
12222 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
12320 # no, it didn't overflow; we have correct result
12375 have taken #
12580 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set
12827 # and an actual fneg performed to see if overflow/underflow would have #
13002 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
13100 # no, it didn't overflow; we have correct result
13715 # no, it didn't overflow; we have correct result
13863 # If you have a 2 DENORMs, then you can just force the j-bit to a one
13865 # If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
13867 # If you have a DENORM and a NORM with opposite signs, then use fcmp_norm, also.
13960 # compute a result. Check if the regular operands would have taken #
14095 # no, it didn't overflow; we have correct result
14123 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14301 # compute a result. Check if the regular operands would have taken #
14456 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14638 # occur. Then, check result exponent to see if exception would have #
14806 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14849 # if the precision is extended, this result could not have come from an
14984 # the ZEROes have opposite signs:
15027 # both operands are INFs. an OPERR will result if the INFs have
15036 # ok, so it's not an OPERR. but, we do have to remember to return the
15091 # occur. Then, check result exponent to see if exception would have #
15259 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set
15302 # if the precision is extended, this result could not have come from an
15436 # the ZEROes have the same signs:
15479 # both operands are INFs. an OPERR will result if the INFs have the
15488 # ok, so it's not an OPERR. but we do have to remember to return
15535 # compute a result. Check if the regular operands would have taken #
15800 # no, it didn't overflow; we have correct result
16347 # have the NAN bit set. #
16388 bne.w fdbcc_bsun # yes; we have an exception
16407 bne.w fdbcc_bsun # yes; we have an exception
16423 bne.w fdbcc_bsun # yes; we have an exception
16430 bne.w fdbcc_bsun # yes; we have an exception
16448 bne.w fdbcc_bsun # yes; we have an exception
16464 bne.w fdbcc_bsun # yes; we have an exception
16483 bne.w fdbcc_bsun # yes; we have an exception
16499 bne.w fdbcc_bsun # yes; we have an exception
16506 bne.w fdbcc_bsun # yes; we have an exception
16524 bne.w fdbcc_bsun # yes; we have an exception
16540 bne.w fdbcc_bsun # yes; we have an exception
16559 bne.w fdbcc_bsun # yes; we have an exception
16573 bne.w fdbcc_bsun # yes; we have an exception
16590 bne.w fdbcc_bsun # yes; we have an exception
16627 bne.w fdbcc_bsun # yes; we have an exception
16640 bne.w fdbcc_bsun # yes; we have an exception
16656 bne.w fdbcc_bsun # yes; we have an exception
16663 bne.w fdbcc_bsun # yes; we have an exception
16679 bne.w fdbcc_bsun # yes; we have an exception
16686 bne.w fdbcc_bsun # yes; we have an exception
16878 # the emulation routine set bsun and BSUN was enabled. have to
16975 # have the NAN bit set. #
17210 # For the IEEE aware tests, we only have to set the result based on the #
17309 # For the IEEE aware tests, we only have to set the result based on the #
17447 # the emulation routine set bsun and BSUN was enabled. have to
17545 # have the NAN bit set. #
17787 # For the IEEE aware tests, we only have to set the result based on the #
17879 # For the IEEE aware tests, we only have to set the result based on the #
18090 # then the address registers have not been updated.
18143 # the emulation routine set bsun and BSUN was enabled. have to
18187 # have our own fcalc_ea() routine here. If an access error is flagged #
19413 # it would make no sense to have a pre-decrement to a7 in supervisor
19610 # longword stacked for the access error exception must have the #
20992 # we'll have to change this, but for now, tough luck!!!
21356 # For a7, if the increment amount is one, then we have to #
21420 # For a7, if the decrement amount is one, then we have to #
21629 # value in d0. The FP number can be DENORM or SNAN so we have to be #
21725 # we have to call the denormalization routine.
21744 # all bit would have been shifted off during the denorm so simply
22230 swap %d1 # have d1.w point to round precision
22740 bclr &0x7, FTEMP_EX(%a0) # clear sgn first; may have residue
22746 # the number may have become zero after rounding. set ccodes accordingly.
22800 bclr &0x7,FTEMP_EX(%a0) # clear sgn first; may have residue
22806 # the number may have become zero after rounding. set ccodes accordingly.
23120 dbf.w %d2,e_gd # if we have used all 3 digits, exit loop
23178 # If all the digits (8) in that long word have been converted (d2=0),
23199 # For adjusted exponents which have an absolute value greater than 27*,
23499 # The operation in A3 above may have set INEX2. #
23524 # The operation in A3 above may have set INEX2. #
23720 # The operation in A3 above may have set INEX2.
23893 # The operation in A3 above may have set INEX2.
23908 # the iscale value would have caused the pwrten calculation
24186 # Since ICTR <> 0, we have already been through one adjustment,
24187 # and shouldn't have another; this is to check if abs(YINT) = 10^LEN
24476 # The 64-bit binary is assumed to have a decimal point before #
24484 # to force the first byte formed to have a 0 in the upper 4 bits. #
24530 subq.l &1,%d0 # for dbf d0 would have LEN+1 passes
24774 # if it's a fmove out instruction, we don't have to fix a7
Indexes created Sat Oct 25 16:10:12 GMT 2025