Lines Matching refs:a6
320 set EXC_A6, EXC_AREGS+(6*4) # offset of saved a6
650 link.w %a6,&-LOCAL_SIZE # init stack frame
652 fsave FP_SRC(%a6) # grab the "busy" frame
654 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
655 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
656 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
659 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
660 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
661 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
663 mov.l %d0,EXC_OPWORD(%a6)
667 btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out?
671 lea FP_SRC(%a6),%a0 # pass: ptr to src op
676 lea FP_SRC(%a6),%a0 # pass: ptr to src op
678 mov.b %d0,STAG(%a6) # maybe NORM,DENORM
683 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
686 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
689 lea FP_DST(%a6),%a0 # pass: ptr to dst op
695 mov.b %d0,DTAG(%a6) # save dst optype tag
699 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
700 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
701 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
702 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
703 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
704 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
707 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
709 mov.b 1+EXC_CMDREG(%a6),%d1
712 andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field
717 lea FP_SRC(%a6),%a0
718 lea FP_DST(%a6),%a1
728 bfextu EXC_CMDREG(%a6){&6:&3},%d0
734 btst &ovfl_bit,FPCR_ENABLE(%a6)
737 btst &inex2_bit,FPCR_ENABLE(%a6)
740 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
741 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
742 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
744 unlk %a6
751 fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
753 mov.w &0xe005,2+FP_SRC(%a6) # save exc status
755 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
756 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
757 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
759 frestore FP_SRC(%a6) # do this after fmovm,other f<op>s!
761 unlk %a6
769 fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
771 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
772 mov.w &0xe001,2+FP_SRC(%a6) # save exc status
774 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
775 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
776 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
778 frestore FP_SRC(%a6) # do this after fmovm,other f<op>s!
780 unlk %a6
788 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
789 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
790 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
793 mov.b &NORM,STAG(%a6) # set src optype tag
796 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
798 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
803 lea FP_SRC(%a6),%a0 # pass ptr to src operand
807 btst &ovfl_bit,FPCR_ENABLE(%a6)
810 btst &inex2_bit,FPCR_ENABLE(%a6)
813 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
814 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
815 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
817 unlk %a6
890 link.w %a6,&-LOCAL_SIZE # init stack frame
892 fsave FP_SRC(%a6) # grab the "busy" frame
894 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
895 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
896 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
899 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
900 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
901 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
903 mov.l %d0,EXC_OPWORD(%a6)
907 btst &0x5,EXC_CMDREG(%a6) # is instr an fmove out?
911 lea FP_SRC(%a6),%a0 # pass: ptr to src op
914 lea FP_SRC(%a6),%a0 # pass: ptr to src op
916 mov.b %d0,STAG(%a6) # maybe NORM,DENORM
921 btst &0x5,1+EXC_CMDREG(%a6) # is op monadic or dyadic?
926 btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
929 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
932 lea FP_DST(%a6),%a0 # pass: ptr to dst op
938 mov.b %d0,DTAG(%a6) # save dst optype tag
942 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
943 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
944 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
945 #$# mov.l FP_DST_EX(%a6),TRAP_DSTOP_EX(%a6)
946 #$# mov.l FP_DST_HI(%a6),TRAP_DSTOP_HI(%a6)
947 #$# mov.l FP_DST_LO(%a6),TRAP_DSTOP_LO(%a6)
950 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
952 mov.b 1+EXC_CMDREG(%a6),%d1
955 andi.l &0x00ff01ff,USER_FPSR(%a6)
960 lea FP_SRC(%a6),%a0
961 lea FP_DST(%a6),%a1
967 bfextu EXC_CMDREG(%a6){&6:&3},%d0
982 btst &unfl_bit,FPCR_ENABLE(%a6)
986 btst &inex2_bit,FPCR_ENABLE(%a6)
990 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
991 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
992 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
994 unlk %a6
1009 btst &unfl_bit,FPSR_EXCEPT(%a6)
1013 fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
1015 mov.w &0xe003,2+FP_SRC(%a6) # save exc status
1017 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1018 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1019 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1021 frestore FP_SRC(%a6) # do this after fmovm,other f<op>s!
1023 unlk %a6
1038 btst &inex2_bit,FPSR_EXCEPT(%a6)
1043 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack
1045 mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
1046 mov.w &0xe001,2+FP_SRC(%a6) # save exc status
1048 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1049 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1050 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1052 frestore FP_SRC(%a6) # do this after fmovm,other f<op>s!
1054 unlk %a6
1062 #$# mov.l FP_SRC_EX(%a6),TRAP_SRCOP_EX(%a6)
1063 #$# mov.l FP_SRC_HI(%a6),TRAP_SRCOP_HI(%a6)
1064 #$# mov.l FP_SRC_LO(%a6),TRAP_SRCOP_LO(%a6)
1067 mov.b &NORM,STAG(%a6) # set src optype tag
1070 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
1072 and.l &0xffff00ff,USER_FPSR(%a6) # zero all but accured field
1077 lea FP_SRC(%a6),%a0 # pass ptr to src operand
1081 btst &unfl_bit,FPCR_ENABLE(%a6)
1084 btst &inex2_bit,FPCR_ENABLE(%a6)
1087 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1088 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1089 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1091 unlk %a6
1215 link.w %a6,&-LOCAL_SIZE # init stack frame
1217 fsave FP_SRC(%a6) # save fp state
1219 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
1220 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
1221 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
1223 btst &0x5,EXC_SR(%a6) # user or supervisor mode?
1227 mov.l %a0,EXC_A7(%a6) # save on stack
1233 lea 0x4+EXC_EA(%a6),%a0 # load old a7'
1234 mov.l %a0,EXC_A7(%a6) # save on stack
1241 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1245 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
1249 clr.b SPCOND_FLG(%a6) # clear special condition flag
1253 btst &0x5,EXC_CMDREG(%a6) # is it an fmove out?
1257 bfextu EXC_CMDREG(%a6){&0:&6},%d0
1264 andi.l &0x00ff00ff,USER_FPSR(%a6) # zero exception field
1272 lea FP_SRC(%a6),%a0 # pass ptr to input
1278 lea FP_SRC(%a6),%a0 # pass: ptr to src op
1285 mov.b %d0,STAG(%a6) # save src optype tag
1287 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1291 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
1293 cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst?
1298 lea FP_DST(%a6),%a0 # pass: ptr to dst op
1304 mov.b %d0,DTAG(%a6) # save dst optype tag
1308 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1310 bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension
1312 lea FP_SRC(%a6),%a0
1313 lea FP_DST(%a6),%a1
1332 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1337 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1342 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1347 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1348 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1349 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1351 unlk %a6
1356 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1370 btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
1374 btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
1399 btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur?
1401 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur?
1412 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status
1414 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1415 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1416 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1418 frestore FP_SRC(%a6) # restore src op
1420 unlk %a6
1441 bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt
1509 bfextu EXC_CMDREG(%a6){&3:&3},%d0
1519 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
1526 mov.w FP_SRC_EX(%a6),%d0 # get exponent
1530 lea FP_SRC(%a6),%a0
1533 mov.b %d0,STAG(%a6)
1537 mov.b &DENORM,STAG(%a6)
1541 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1543 lea FP_SRC(%a6),%a0 # pass ptr to src operand
1545 mov.l (%a6),EXC_A6(%a6) # in case a6 changes
1560 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
1565 mov.l EXC_A6(%a6),(%a6) # in case a6 changed
1572 btst &0x5,EXC_SR(%a6)
1575 mov.l EXC_A7(%a6),%a0 # restore a7
1579 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1580 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1581 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1583 unlk %a6
1593 cmpi.b SPCOND_FLG(%a6),&mda7_flg
1601 fmovm.x &0x80,FP_SRC(%a6) # put answer on stack
1603 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1604 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1605 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1607 mov.l (%a6),%a6 # restore frame pointer
1625 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
1632 btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
1636 btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
1686 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1687 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1688 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1690 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd8
1691 mov.w &0xe006,2+FP_SRC(%a6)
1693 frestore FP_SRC(%a6)
1695 unlk %a6
1701 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1702 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1703 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1705 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0
1706 mov.w &0xe004,2+FP_SRC(%a6)
1708 frestore FP_SRC(%a6)
1710 unlk %a6
1716 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
1718 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1719 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1720 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1722 mov.w &0x30d4,EXC_VOFF(%a6) # vector offset = 0xd4
1723 mov.w &0xe005,2+FP_SRC(%a6)
1725 frestore FP_SRC(%a6) # restore EXOP
1727 unlk %a6
1736 mov.l EXC_A6(%a6),(%a6) # restore a6
1738 btst &0x5,EXC_SR(%a6)
1741 mov.l EXC_A7(%a6),%a0 # restore a7 whether we need
1745 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
1747 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1748 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1749 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1751 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc
1752 mov.w &0xe003,2+FP_SRC(%a6)
1754 frestore FP_SRC(%a6) # restore EXOP
1756 unlk %a6
1761 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the <ea> mode -(sp)?
1768 fmovm.x &0x80,FP_SRC(%a6) # put answer on stack
1769 fmovm.x &0x40,FP_DST(%a6) # put EXOP on stack
1771 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1772 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1773 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1775 mov.w &0x30cc,EXC_VOFF(%a6) # vector offset = 0xcc
1776 mov.w &0xe003,2+FP_DST(%a6)
1778 frestore FP_DST(%a6) # restore EXOP
1780 mov.l (%a6),%a6 # restore frame pointer
1797 fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
1799 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1800 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1801 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1803 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
1804 mov.w &0xe001,2+FP_SRC(%a6)
1806 frestore FP_SRC(%a6) # restore EXOP
1808 unlk %a6
1820 andi.l &0x0ff00ff,USER_FPSR(%a6) # zero exception field
1827 lea FP_SRC(%a6),%a0 # pass ptr to src
1830 mov.b %d0,STAG(%a6) # save src optype tag
1832 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1836 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
1838 cmpi.b 1+EXC_CMDREG(%a6),&0x3a # is operation an ftst?
1843 lea FP_DST(%a6),%a0 # pass: ptr to dst op
1849 mov.b %d0,DTAG(%a6) # save dst optype tag
1853 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1855 bfextu 1+EXC_CMDREG(%a6){&1:&7},%d1 # extract extension
1857 lea FP_SRC(%a6),%a0
1858 lea FP_DST(%a6),%a1
1877 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
1882 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1887 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
1892 btst &0x5,EXC_SR(%a6) # user or supervisor?
1895 mov.l EXC_A7(%a6),%a0 # update user a7
1899 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1900 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1901 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1903 unlk %a6 # unravel stack frame
1914 btst &mia7_bit,SPCOND_FLG(%a6) # was ea mode (a7)+
1917 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1918 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1919 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1921 unlk %a6 # unravel stack frame
1934 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set
1948 btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
1952 btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
1977 btst &unfl_bit,FPSR_EXCEPT(%a6) # did disabled underflow occur?
1979 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did disabled overflow occur?
1989 btst &0x5,EXC_SR(%a6) # user or supervisor?
1992 mov.l EXC_A7(%a6),%a0 # update user a7
1996 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6)
1998 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
1999 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2000 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2002 frestore FP_SRC(%a6) # restore src op
2004 unlk %a6
2024 a6)
2027 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6)
2029 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2030 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2031 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2033 frestore FP_SRC(%a6) # restore src op
2035 unlk %a6 # unravel stack frame
2078 and.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
2083 bfextu EXC_CMDREG(%a6){&6:&3},%d0
2088 lea FP_SRC(%a6),%a0
2095 mov.b %d0,STAG(%a6) # save src optype tag
2098 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
2100 lea FP_SRC(%a6),%a0 # pass ptr to src operand
2102 mov.l (%a6),EXC_A6(%a6) # in case a6 changes
2117 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
2121 mov.l EXC_A6(%a6),(%a6) # restore a6
2123 btst &0x5,EXC_SR(%a6) # user or supervisor?
2126 mov.l EXC_A7(%a6),%a0 # update user a7
2130 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2131 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2132 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2134 unlk %a6 # unravel stack frame
2145 btst &mda7_bit,SPCOND_FLG(%a6) # was ea mode -(a7)
2148 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2149 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2150 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2152 mov.l (%a6),%a6 # restore frame pointer
2170 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled
2174 mov.l EXC_A6(%a6),(%a6) # restore a6
2184 btst &0x5,EXC_SR(%a6)
2187 mov.l EXC_A7(%a6),%a0
2192 cmpi.b SPCOND_FLG(%a6),&mda7_flg
2198 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2199 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2200 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2202 mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0
2203 mov.w &0xe006,2+FP_SRC(%a6) # set fsave status
2205 frestore FP_SRC(%a6) # restore src operand
2207 mov.l (%a6),%a6 # restore frame pointer
2224 btst &0x5,EXC_SR(%a6)
2227 mov.l EXC_A7(%a6),%a0
2232 cmpi.b SPCOND_FLG(%a6),&mda7_flg
2238 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2239 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2240 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2242 mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0
2243 mov.w &0xe004,2+FP_SRC(%a6) # set fsave status
2245 frestore FP_SRC(%a6) # restore src operand
2247 mov.l (%a6),%a6 # restore frame pointer
2264 btst &0x5,EXC_SR(%a6)
2267 mov.l EXC_A7(%a6),%a0
2272 cmpi.b SPCOND_FLG(%a6),&mda7_flg
2278 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
2279 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2280 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2282 mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
2283 mov.w &0xe001,2+FP_SRC(%a6) # set fsave status
2285 frestore FP_SRC(%a6) # restore src operand
2287 mov.l (%a6),%a6 # restore frame pointer
2312 bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier
2320 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent
2327 mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man)
2330 mov.l %d1,FP_SRC_HI(%a6) # insert new hi(man)
2331 andi.w &0x8000,FP_SRC_EX(%a6) # clear old exponent
2332 ori.w &0x3f80,FP_SRC_EX(%a6) # insert new "skewed" exponent
2337 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent
2343 tst.b FP_SRC_EX(%a6) # make "internal format"
2344 smi.b 0x2+FP_SRC(%a6)
2345 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign
2347 lea FP_SRC(%a6),%a0 # pass ptr to src op
2351 tst.b 0x2+FP_SRC(%a6) # is sign set?
2355 bset &0x7,FP_SRC_HI(%a6) # set j-bit
2356 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent
2363 btst &0x5,EXC_SR(%a6)
2365 mov.l 0x0(%a0),FP_DST_EX(%a6)
2366 mov.l 0x4(%a0),FP_DST_HI(%a6)
2367 mov.l 0x8(%a0),FP_DST_LO(%a6)
2473 link %a6,&-LOCAL_SIZE # init stack frame
2475 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2476 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
2477 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
2480 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
2482 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
2483 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
2485 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2512 andi.l &0x00ff00ff,USER_FPSR(%a6)
2518 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data>
2519 lea FP_SRC(%a6),%a1 # pass: ptr to super addr
2530 mov.l EXC_EXTWPTR(%a6),%a0 # pass: ptr to #<data>
2531 lea FP_SRC(%a6),%a1 # pass: ptr to super dst
2539 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp
2545 mov.b 3+FP_SRC(%a6),%d0 # get byte 4
2548 tst.l FP_SRC_HI(%a6) # is lw 2 zero?
2550 tst.l FP_SRC_LO(%a6) # is lw 3 zero?
2553 lea FP_SRC(%a6),%a0 # pass: ptr to packed op
2555 fmovm.x &0x80,FP_SRC(%a6) # make this the srcop
2558 addi.l &0xc,EXC_EXTWPTR(%a6) # update extension word pointer
2561 lea FP_SRC(%a6),%a0 # pass: ptr to src op
2563 mov.b %d0,STAG(%a6) # could be ANYTHING!!!
2567 mov.b %d0,STAG(%a6) # set new optype tag
2569 clr.b STORE_FLG(%a6) # clear "store result" boolean
2571 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
2573 btst &0x4,1+EXC_CMDREG(%a6) # is operation fsincos,ftst,fcmp?
2577 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno
2580 lea FP_DST(%a6),%a0 # pass: ptr to dst op
2582 mov.b %d0,DTAG(%a6) # could be ANYTHING!!!
2586 mov.b %d0,DTAG(%a6) # set new optype tag
2591 btst &0x3,1+EXC_CMDREG(%a6) # is operation fsincos?
2595 st STORE_FLG(%a6) # don't store a final result
2596 btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp?
2601 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec
2603 mov.b 1+EXC_CMDREG(%a6),%d1
2609 lea FP_SRC(%a6),%a0
2610 lea FP_DST(%a6),%a1
2629 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
2635 tst.b STORE_FLG(%a6) # does this op store a result?
2639 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno
2643 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC"
2644 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame
2646 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2647 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2648 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2650 unlk %a6 # unravel the frame
2658 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set
2664 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur?
2668 btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled?
2682 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur?
2684 btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur?
2688 mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6)
2696 mov.w &0xe005,2+FP_SRC(%a6)
2700 mov.w &0xe003,2+FP_SRC(%a6)
2703 mov.l EXC_PC(%a6),USER_FPIAR(%a6) # set FPIAR to "Current PC"
2704 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set "Next PC" in exc frame
2706 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2707 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2708 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2710 frestore FP_SRC(%a6) # restore exceptional state
2712 unlk %a6 # unravel the frame
2751 btst &0x5,EXC_SR(%a6) # user or supervisor mode
2756 mov.l %a0,EXC_A7(%a6) # store current a7
2758 mov.l EXC_A7(%a6),%a0 # load possibly new a7
2763 clr.b SPCOND_FLG(%a6)
2764 lea 0x2+EXC_VOFF(%a6),%a0
2765 mov.l %a0,EXC_A7(%a6)
2768 cmpi.b SPCOND_FLG(%a6),&mda7_flg
2770 cmpi.b SPCOND_FLG(%a6),&mia7_flg
2778 btst &0x7,EXC_SR(%a6)
2781 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0)
2782 mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0)
2783 mov.w &0x00f0,(EXC_VOFF,%a6,%d0)
2785 lea (EXC_SR,%a6,%d0),%a0
2786 mov.l %a0,EXC_SR(%a6)
2788 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2789 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2790 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2792 unlk %a6
2797 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0)
2798 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0)
2799 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0)
2800 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0)
2802 lea (EXC_SR-0x4,%a6,%d0),%a0
2803 mov.l %a0,EXC_SR(%a6)
2805 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2806 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2807 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2809 unlk %a6
2815 mov.b %d1,EXC_VOFF(%a6) # store strg
2816 mov.b %d0,0x1+EXC_VOFF(%a6) # store size
2818 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2819 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2820 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2822 mov.l (%a6),-(%sp) # make a copy of a6
2825 mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC
2828 mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size
2831 btst &0x7,EXC_SR(%a6) # is trace enabled?
2834 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0)
2835 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0)
2836 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0)
2837 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0)
2839 pea (%a6,%d0) # create final sp
2843 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0)
2844 mov.l (%sp)+,(EXC_PC,%a6,%d0)
2845 mov.w &0x00f0,(EXC_VOFF,%a6,%d0)
2847 pea (0x4,%a6,%d0) # create final sp
2851 mov.b EXC_VOFF(%a6),%d1 # fetch strg
2855 fmovm.x &0x80,(0x4+0x8,%a6,%d0)
2860 fmovm.x &0x40,(0x4+0x8,%a6,%d0)
2865 fmovm.x &0x20,(0x4+0x8,%a6,%d0)
2870 fmovm.x &0x10,(0x4+0x8,%a6,%d0)
2875 fmovm.x &0x08,(0x4+0x8,%a6,%d0)
2880 fmovm.x &0x04,(0x4+0x8,%a6,%d0)
2885 fmovm.x &0x02,(0x4+0x8,%a6,%d0)
2890 fmovm.x &0x01,(0x4+0x8,%a6,%d0)
2894 mov.l 0xc(%sp),%a6
2907 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2908 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2909 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2911 btst &0x7,EXC_SR(%a6) # is trace on?
2914 mov.l EXC_EXTWPTR(%a6),EXC_PC(%a6) # set Next PC
2916 unlk %a6 # unravel the frame
2939 # -restore a6 (not with unlk)
2940 # -shift stack frame down over where old a6 used to be
2943 mov.l (%a6),%a6 # restore frame pointer
2962 link %a6,&-LOCAL_SIZE # init stack frame
2964 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2967 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
2968 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
2969 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
2971 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD
2997 mov.l EXC_EXTWPTR(%a6),%d0
2998 sub.l EXC_PC(%a6),%d0
3000 mov.w %d0,EXC_VOFF(%a6) # store stack shift value
3002 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3004 unlk %a6
3028 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3029 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3031 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3033 unlk %a6
3051 lea -LOCAL_SIZE(%a6),%sp
3056 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3059 mov.l (%a6),%a6
3118 link.w %a6,&-LOCAL_SIZE # init stack frame
3120 fsave FP_SRC(%a6) # grab the "busy" frame
3122 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3123 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3124 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3127 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3129 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3130 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3132 mov.l %d0,EXC_OPWORD(%a6)
3144 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3148 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3149 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3150 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3152 frestore FP_SRC(%a6)
3154 unlk %a6
3176 mov.w FP_SRC_EX(%a6),%d1 # fetch exponent
3181 tst.l FP_SRC_LO(%a6)
3183 mov.l FP_SRC_HI(%a6),%d1
3187 mov.l FP_SRC_HI(%a6),L_SCR1(%a6)
3192 tst.b FP_SRC_EX(%a6)
3196 mov.l %d1,L_SCR1(%a6)
3200 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3215 mov.b L_SCR1(%a6),%d0 # load positive default result
3218 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3231 mov.w L_SCR1(%a6),%d0 # load positive default result
3234 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3247 mov.l L_SCR1(%a6),%d0 # load positive default result
3250 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3314 link.w %a6,&-LOCAL_SIZE # init stack frame
3316 fsave FP_SRC(%a6) # grab the "busy" frame
3318 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3319 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3320 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3323 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3325 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3326 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3328 mov.l %d0,EXC_OPWORD(%a6)
3340 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3344 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3345 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3346 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3348 frestore FP_SRC(%a6)
3350 unlk %a6
3370 mov.b 1+EXC_OPWORD(%a6),%d1 # extract <ea> mode,reg
3385 mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN
3389 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3402 mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN
3406 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3419 mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN
3423 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3438 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign
3441 mov.l FP_SRC_HI(%a6),%d1 # load mantissa
3444 mov.l EXC_EA(%a6),%a0 # pass: <ea> of default result
3452 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign
3456 mov.l FP_SRC_HI(%a6),%d1 # load mantissa
3465 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign
3468 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa
3469 mov.l %d0,FP_SCR0_EX(%a6) # store to temp space
3472 or.l %d1,FP_SCR0_EX(%a6) # create dbl hi
3473 mov.l FP_SRC_HI(%a6),%d1 # load hi mantissa
3476 mov.l %d1,FP_SCR0_HI(%a6) # store to temp space
3477 mov.l FP_SRC_LO(%a6),%d1 # load lo mantissa
3479 or.l %d1,FP_SCR0_HI(%a6) # create dbl lo
3480 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
3481 mov.l EXC_EA(%a6),%a1 # pass: dst addr
3494 clr.b SPCOND_FLG(%a6) # clear special case flag
3496 mov.w FP_SRC_EX(%a6),FP_SCR0_EX(%a6)
3497 clr.w 2+FP_SCR0(%a6)
3498 mov.l FP_SRC_HI(%a6),%d0
3500 mov.l %d0,FP_SCR0_HI(%a6)
3501 mov.l FP_SRC_LO(%a6),FP_SCR0_LO(%a6)
3503 btst &0x5,EXC_SR(%a6) # supervisor mode exception?
3507 mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea()
3508 mov.l (%a6),EXC_A6(%a6)
3512 mov.l %a0,EXC_EA(%a6) # stack correct <ea>
3514 mov.l EXC_A7(%a6),%a0
3516 mov.l EXC_A6(%a6),(%a6)
3519 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
3529 mov.l (%a6),EXC_A6(%a6)
3533 mov.l %a0,EXC_EA(%a6) # stack correct <ea>
3535 mov.l EXC_A6(%a6),(%a6)
3537 cmpi.b SPCOND_FLG(%a6),&mda7_flg # is <ea> mode -(a7)?
3541 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3542 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3543 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3545 frestore FP_SRC(%a6)
3547 mov.l EXC_A6(%a6),%a6 # restore frame pointer
3606 link.w %a6,&-LOCAL_SIZE # init stack frame
3608 fsave FP_SRC(%a6) # grab the "busy" frame
3610 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3611 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3612 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3615 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3617 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3618 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3620 mov.l %d0,EXC_OPWORD(%a6)
3633 cmpi.w FP_SRC_EX(%a6),&0x401e # is exponent 0x401e?
3636 fmov.l FP_SRC_HI(%a6),%fp0 # load integer src
3637 fmov.x %fp0,FP_SRC(%a6) # store integer as extended precision
3638 mov.w &0xe001,0x2+FP_SRC(%a6)
3641 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3649 andi.l &0x00ff01ff,USER_FPSR(%a6) # zero all but accured field
3654 bfextu EXC_EXTWORD(%a6){&0:&6},%d1 # extract upper 6 of cmdreg
3658 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3660 mov.b %d0,STAG(%a6) # maybe NORM,DENORM
3665 btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
3668 btst &0x4,1+EXC_CMDREG(%a6) # is operation an fsincos?
3671 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
3674 lea FP_DST(%a6),%a0 # pass: ptr to dst op
3680 mov.b %d0,DTAG(%a6) # save dst optype tag
3684 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode
3686 mov.b 1+EXC_CMDREG(%a6),%d1
3689 lea FP_SRC(%a6),%a0
3690 lea FP_DST(%a6),%a1
3697 bfextu EXC_CMDREG(%a6){&6:&3},%d0
3701 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3702 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3703 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3705 frestore FP_SRC(%a6)
3707 unlk %a6
3712 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode
3713 mov.b 1+EXC_CMDREG(%a6),%d1
3734 mov.b &NORM,STAG(%a6) # src is a NORM
3737 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode
3739 andi.l &0xffff00ff,USER_FPSR(%a6) # zero exception field
3741 lea FP_SRC(%a6),%a0 # pass ptr to src operand
3780 link.w %a6,&-LOCAL_SIZE # init stack frame
3782 fsave FP_SRC(%a6) # grab the "busy" frame
3784 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3785 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3786 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3789 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
3791 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3792 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3794 mov.l %d0,EXC_OPWORD(%a6)
3802 lea FP_SRC(%a6),%a0 # pass: ptr to src op
3806 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3807 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3808 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3810 frestore FP_SRC(%a6)
3812 unlk %a6
3870 link.w %a6,&-LOCAL_SIZE # init stack frame
3872 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3874 mov.l EXC_PC(%a6),EXC_EXTWPTR(%a6)
3875 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
3876 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
3899 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3901 unlk %a6
3913 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3915 unlk %a6
3927 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3929 unlk %a6
4028 link.w %a6,&-LOCAL_SIZE # init stack frame
4030 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
4031 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
4032 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1
4034 btst &0x5,EXC_SR(%a6) # user mode exception?
4040 mov.l %a0,EXC_A7(%a6) # store in stack frame
4046 lea 4+EXC_EA(%a6),%a0 # load old a7'
4047 mov.l %a0,EXC_A7(%a6) # store a7'
4048 mov.l %a0,OLD_A7(%a6) # make a copy
4053 mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
4055 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
4056 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
4058 mov.l %d0,EXC_OPWORD(%a6)
4065 clr.b SPCOND_FLG(%a6) # clear "special case" flag
4079 clr.b STORE_FLG(%a6) # clear "store result" flag
4082 andi.l &0x00ff00ff,USER_FPSR(%a6)
4092 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode
4094 mov.b 1+EXC_CMDREG(%a6),%d1
4097 or.b STAG(%a6),%d1 # insert src optag bits
4099 lea FP_DST(%a6),%a1 # pass dst ptr in a1
4100 lea FP_SRC(%a6),%a0 # pass src ptr in a0
4106 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
4110 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch Dn
4114 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4115 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4116 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4119 cmpi.b SPCOND_FLG(%a6),&mia7_flg # was the ea mode (sp)+ ?
4122 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the ea mode -(sp) ?
4126 unlk %a6
4143 btst &0x5,EXC_SR(%a6) # supervisor or user mode?
4147 mov.l EXC_A7(%a6),%a0
4158 mov.l EXC_A7(%a6),%d0 # load new a7'
4159 sub.l OLD_A7(%a6),%d0 # subtract old a7'
4160 mov.l 0x2+EXC_PC(%a6),(0x2+EXC_PC,%a6,%d0) # shift stack frame
4161 mov.l EXC_SR(%a6),(EXC_SR,%a6,%d0) # shift stack frame
4162 mov.w %d0,EXC_SR(%a6) # store incr number
4165 unlk %a6
4175 mov.b FPCR_MODE(%a6),%d0
4176 mov.b 1+EXC_CMDREG(%a6),%d1
4190 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set
4197 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur?
4202 btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled?
4219 btst &ovfl_bit,FPSR_EXCEPT(%a6) # did overflow occur?
4221 btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur?
4231 mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6)
4241 mov.w &0xe005,2+FP_SRC(%a6)
4247 mov.w &0xe003,2+FP_SRC(%a6)
4252 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4253 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4254 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4256 frestore FP_SRC(%a6) # insert exceptional status
4287 cmpi.b SPCOND_FLG(%a6),&fbsun_flg # is enabled bsun occurring?
4290 cmpi.b SPCOND_FLG(%a6),&ftrapcc_flg # should a trap occur?
4309 mov.l USER_FPIAR(%a6),EXC_EA(%a6) # Address = Current PC
4310 mov.w &0x201c,EXC_VOFF(%a6) # Vector Offset = 0x01c
4312 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4313 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4314 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4316 unlk %a6
4324 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
4325 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
4335 cmpi.b SPCOND_FLG(%a6),&fbsun_flg # is enabled bsun occurring?
4349 cmpi.b SPCOND_FLG(%a6),&fbsun_flg # is enabled bsun occurring?
4352 btst &0x5,EXC_SR(%a6) # yes; is it a user mode exception?
4356 mov.l EXC_A7(%a6),%a0 # yes; set new USP
4368 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was a7 modified?
4371 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4372 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4373 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4375 unlk %a6
4413 mov.w &0x00c0,2+EXC_EA(%a6) # Fmt = 0x0; Vector Offset = 0x0c0
4414 mov.l USER_FPIAR(%a6),EXC_VOFF(%a6) # PC = Current PC
4415 mov.w EXC_SR(%a6),2+EXC_PC(%a6) # shift SR "up"
4417 mov.w &0xe000,2+FP_SRC(%a6) # bsun exception enabled
4419 a6),&0xc0 # restore fp0-fp1
4420 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4421 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4423 frestore FP_SRC(%a6) # restore bsun exception
4425 unlk %a6
4440 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
4441 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4442 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4444 unlk %a6
4987 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
4988 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
4989 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
4991 mov.l USER_FPIAR(%a6),EXC_PC(%a6) # store current PC
4993 unlk %a6
5131 mov.l &0,ADJN(%a6) # yes; SET ADJN TO 0
5137 mov.l &1,ADJN(%a6) # yes; SET ADJN TO 1
5144 fmov.x %fp0,X(%a6) # save input at X
5168 fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER
5170 mov.l INT(%a6),%d1 # make a copy of N
5183 mov.l INT(%a6),%d1
5184 add.l ADJN(%a6),%d1 # SEE IF D0 IS ODD OR EVEN
5200 fmov.x %fp0,X(%a6) # X IS R
5212 eor.l %d1,X(%a6) # X IS NOW R'= SGN*R
5230 fmul.x X(%a6),%fp0 # R'*S
5239 fadd.x X(%a6),%fp0 # last inst - possible exception set
5262 fmov.x %fp0,X(%a6) # X IS S
5269 eor.l %d1,X(%a6) # X IS NOW S'= SGN*S
5275 mov.l %d1,POSNEG1(%a6)
5296 fmul.x X(%a6),%fp0
5301 fadd.s POSNEG1(%a6),%fp0 # last inst - possible exception set
5314 mov.l ADJN(%a6),%d1
5321 # mov.w &0x0000,XDCARE(%a6) # JUST IN CASE
5325 fmov.x X(%a6),%fp0 # last inst - possible exception set
5352 mov.l &4,ADJN(%a6)
5355 fmov.x %fp0,X(%a6)
5380 fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER
5382 mov.l INT(%a6),%d1
5392 mov.l INT(%a6),%d1
5401 fmov.x %fp0,RPRIME(%a6)
5415 fadd.d SINA6(%pc),%fp1 # A6+SA7
5418 fmul.x %fp0,%fp1 # S(A6+SA7)
5419 eor.l %d2,RPRIME(%a6)
5424 mov.l &0x3F800000,POSNEG1(%a6)
5425 eor.l %d1,POSNEG1(%a6)
5427 fadd.d SINA5(%pc),%fp1 # A5+S(A6+SA7)
5430 fmul.x %fp0,%fp1 # S(A5+S(A6+SA7))
5432 fmov.x %fp0,SPRIME(%a6)
5434 fadd.d SINA4(%pc),%fp1 # A4+S(A5+S(A6+SA7))
5435 eor.l %d1,SPRIME(%a6)
5459 fmul.x RPRIME(%a6),%fp1 # R'S(A1+...)
5461 fmul.x SPRIME(%a6),%fp0 # S'(B1+S(B2+...))
5466 fadd.x RPRIME(%a6),%fp1 # COS(X)
5468 fadd.s POSNEG1(%a6),%fp0 # SIN(X)
5475 fmov.x %fp0,RPRIME(%a6)
5482 fmov.x %fp0,SPRIME(%a6)
5489 fadd.d SINA6(%pc),%fp2 # A6+SA7
5491 eor.l %d1,RPRIME(%a6)
5492 eor.l %d1,SPRIME(%a6)
5497 mov.l %d1,POSNEG1(%a6)
5499 fmul.x %fp0,%fp2 # S(A6+SA7)
5502 fadd.d SINA5(%pc),%fp2 # A5+S(A6+SA7)
5505 fmul.x %fp0,%fp2 # S(A5+S(A6+SA7))
5508 fadd.d SINA4(%pc),%fp2 # A4+S(A5+S(A6+SA7))
5533 fmul.x RPRIME(%a6),%fp0 # R'S(A1+...)
5534 fmul.x SPRIME(%a6),%fp1 # S'(B1+S(B2+...))
5539 fadd.s POSNEG1(%a6),%fp1 # COS(X)
5541 fadd.x RPRIME(%a6),%fp0 # SIN(X)
5553 # mov.w &0x0000,XDCARE(%a6)
5561 fmov.x X(%a6),%fp0
5593 mov.w &0x7ffe,FP_SCR0_EX(%a6)
5594 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6)
5595 clr.l FP_SCR0_LO(%a6)
5598 mov.w &0x7fdc,FP_SCR1_EX(%a6)
5599 mov.l &0x85a308d3,FP_SCR1_HI(%a6)
5600 clr.l FP_SCR1_LO(%a6)
5605 or.b &0x80,FP_SCR0_EX(%a6) # positive arg
5606 or.b &0x80,FP_SCR1_EX(%a6)
5608 fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact
5610 fadd.x FP_SCR1(%a6),%fp0 # low part of reduction
5612 fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument.
5618 fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2
5619 mov.w INARG(%a6),%d1
5627 mov.b &0,ENDFLAG(%a6)
5631 mov.b &1,ENDFLAG(%a6)
5643 mov.l &0xA2F9836E,FP_SCR0_HI(%a6)
5644 mov.l &0x4E44152A,FP_SCR0_LO(%a6)
5645 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI)
5648 fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI)
5659 mov.l %d2,TWOTO63(%a6)
5660 fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED
5661 fsub.s TWOTO63(%a6),%fp2 # fp2 = N
5668 mov.w %d2,FP_SCR0_EX(%a6)
5669 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6)
5670 clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1
5673 mov.w %d1,FP_SCR1_EX(%a6)
5674 mov.l &0x85A308D3,FP_SCR1_HI(%a6)
5675 clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2
5677 mov.b ENDFLAG(%a6),%d1
5682 fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1
5684 fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2
5711 fmov.l %fp2,INT(%a6)
5715 mov.l ADJN(%a6),%d1
6024 mov.w &0x7ffe,FP_SCR0_EX(%a6)
6025 mov.l &0xc90fdaa2,FP_SCR0_HI(%a6)
6026 clr.l FP_SCR0_LO(%a6)
6029 mov.w &0x7fdc,FP_SCR1_EX(%a6)
6030 mov.l &0x85a308d3,FP_SCR1_HI(%a6)
6031 clr.l FP_SCR1_LO(%a6)
6036 or.b &0x80,FP_SCR0_EX(%a6) # positive arg
6037 or.b &0x80,FP_SCR1_EX(%a6)
6039 fadd.x FP_SCR0(%a6),%fp0 # high part of reduction is exact
6041 fadd.x FP_SCR1(%a6),%fp0 # low part of reduction
6043 fadd.x FP_SCR1(%a6),%fp1 # fp0/fp1 are reduced argument.
6049 fmov.x %fp0,INARG(%a6) # +-2**K * F, 1 <= F < 2
6050 mov.w INARG(%a6),%d1
6058 mov.b &0,ENDFLAG(%a6)
6062 mov.b &1,ENDFLAG(%a6)
6074 mov.l &0xA2F9836E,FP_SCR0_HI(%a6)
6075 mov.l &0x4E44152A,FP_SCR0_LO(%a6)
6076 mov.w %d2,FP_SCR0_EX(%a6) # FP_SCR0 = 2**(-L)*(2/PI)
6079 fmul.x FP_SCR0(%a6),%fp2 # fp2 = X * 2**(-L)*(2/PI)
6090 mov.l %d2,TWOTO63(%a6)
6091 fadd.s TWOTO63(%a6),%fp2 # THE FRACTIONAL PART OF FP1 IS ROUNDED
6092 fsub.s TWOTO63(%a6),%fp2 # fp2 = N
6099 mov.w %d2,FP_SCR0_EX(%a6)
6100 mov.l &0xC90FDAA2,FP_SCR0_HI(%a6)
6101 clr.l FP_SCR0_LO(%a6) # FP_SCR0 = 2**(L) * Piby2_1
6104 mov.w %d1,FP_SCR1_EX(%a6)
6105 mov.l &0x85A308D3,FP_SCR1_HI(%a6)
6106 clr.l FP_SCR1_LO(%a6) # FP_SCR1 = 2**(L) * Piby2_2
6108 mov.b ENDFLAG(%a6),%d1
6113 fmul.x FP_SCR0(%a6),%fp4 # fp4 = W = N*P1
6115 fmul.x FP_SCR1(%a6),%fp5 # fp5 = w = N*P2
6142 fmov.l %fp2,INT(%a6)
6146 mov.l INT(%a6),%d1
6361 fmov.x %fp0,X(%a6)
6396 and.l &0xF8000000,XFRAC(%a6) # FIRST 5 BITS
6397 or.l &0x04000000,XFRAC(%a6) # SET 6-TH BIT TO 1
6398 mov.l &0x00000000,XFRACLO(%a6) # LOCATION OF X IS NOW F
6401 fmul.x X(%a6),%fp1 # FP1 IS X*F, NOTE THAT X*F > 0
6402 fsub.x X(%a6),%fp0 # FP0 IS X-F
6420 mov.l (%a1)+,ATANF(%a6)
6421 mov.l (%a1)+,ATANFHI(%a6)
6422 mov.l (%a1)+,ATANFLO(%a6) # ATANF IS NOW ATAN(|F|)
6423 mov.l X(%a6),%d1 # LOAD SIGN AND EXPO. AGAIN
6425 or.l %d1,ATANF(%a6) # ATANF IS NOW SIGN(F)*ATAN(|F|)
6455 fadd.x ATANF(%a6),%fp0 # ATAN(X)
6498 fmul.x X(%a6),%fp0 # X*Y
6507 fadd.x X(%a6),%fp0
6515 fmov.x X(%a6),%fp0 # last inst - possible exception set
6539 fmov.x %fp1,X(%a6) # X IS REALLY X'
6557 fmul.x X(%a6),%fp0 # X'*Y
6563 fadd.x X(%a6),%fp0
7028 # p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) #
7031 # and A6 are single precision; A2, A3 and A4 are double #
7038 # p = [ R*S*(A2 + S*(A4 + S*A6)) ] + #
7241 mov.l &0,ADJFLAG(%a6)
7246 mov.l %d1,L_SCR1(%a6) # save N temporarily
7250 mov.l L_SCR1(%a6),%d1
7253 mov.w L2(%pc),L_SCR1(%a6) # prefetch L2, no need in CB
7284 mov.w %d1,SCALE(%a6) # SCALE is 2^(M) in extended
7285 mov.l &0x80000000,SCALE+4(%a6)
7286 clr.l SCALE+8(%a6)
7308 mov.l ADJFLAG(%a6),%d1
7314 fmul.x ADJSCALE(%a6),%fp0
7318 fmul.x SCALE(%a6),%fp0 # multiply 2^(M)
7338 mov.l &1,ADJFLAG(%a6)
7342 mov.l %d1,L_SCR1(%a6) # save N temporarily
7346 mov.l L_SCR1(%a6),%d1
7348 mov.l %d1,L_SCR1(%a6) # save K temporarily
7350 sub.l %d1,L_SCR1(%a6) # a1 is M
7352 mov.w %d1,ADJSCALE(%a6) # ADJSCALE := 2^(M1)
7353 mov.l &0x80000000,ADJSCALE+4(%a6)
7354 clr.l ADJSCALE+8(%a6)
7355 mov.l L_SCR1(%a6),%d1 # D0 is M
7410 mov.l %d1,L_SCR1(%a6) # save N temporarily
7414 mov.l L_SCR1(%a6),%d1
7416 mov.l %d1,L_SCR1(%a6) # save a copy of M
7430 #-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*(A5 + R*A6)))))
7432 #--[R*S*(A2+S*(A4+S*A6))] + [R+S*(A1+S*(A3+S*A5))]
7437 fmov.s &0x3950097B,%fp2 # fp2 IS a6
7439 fmul.x %fp1,%fp2 # fp2 IS S*A6
7443 fadd.d EM1A4(%pc),%fp2 # fp2 IS A4+S*A6
7445 mov.w %d1,SC(%a6) # SC is 2^(M) in extended
7446 mov.l &0x80000000,SC+4(%a6)
7447 clr.l SC+8(%a6)
7449 fmul.x %fp1,%fp2 # fp2 IS S*(A4+S*A6)
7450 mov.l L_SCR1(%a6),%d1 # D0 is M
7454 fadd.d EM1A2(%pc),%fp2 # fp2 IS A2+S*(A4+S*A6)
7457 fmul.x %fp1,%fp2 # fp2 IS S*(A2+S*(A4+S*A6))
7459 mov.w %d1,ONEBYSC(%a6) # OnebySc is -2^(-M)
7460 mov.l &0x80000000,ONEBYSC+4(%a6)
7461 clr.l ONEBYSC+8(%a6)
7464 fmul.x %fp0,%fp2 # fp2 IS R*S*(A2+S*(A4+S*A6))
7478 mov.l L_SCR1(%a6),%d1 # retrieve M
7483 fadd.x ONEBYSC(%a6),%fp1 # fp1 is t+OnebySc
7495 fadd.x ONEBYSC(%a6),%fp0 # OnebySc + (T+(p+t))
7501 fadd.x ONEBYSC(%a6),%fp1 # fp1 is T+OnebySc
7507 fmul.x SC(%a6),%fp0
7520 mov.l &0x80010000,SC(%a6) # SC is -2^(-16382)
7521 mov.l &0x80000000,SC+4(%a6)
7522 clr.l SC+8(%a6)
7526 fadd.x SC(%a6),%fp0
7533 mov.l &0x80010000,SC(%a6)
7534 mov.l &0x80000000,SC+4(%a6)
7535 clr.l SC+8(%a6)
7536 fadd.x SC(%a6),%fp0
7640 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7649 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7659 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy to tmp loc
7660 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy to tmp loc
7661 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
7662 fmov.x FP_SCR0(%a6),%fp0 # put new value back in fp0
7667 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
7969 fmov.x %fp0,X(%a6)
7972 mov.l %d1,X(%a6)
7982 mov.l X(%a6),%d1
7983 mov.l %d1,SGN(%a6)
7986 mov.l %d1,X(%a6)
7987 and.l &0x80000000,SGN(%a6)
7988 fmov.x X(%a6),%fp0 # FP0 IS Y = 2|X|
8000 mov.l SGN(%a6),%d1
8001 fmov.x %fp1,V(%a6)
8002 eor.l %d1,V(%a6)
8005 fdiv.x V(%a6),%fp0
8019 mov.l X(%a6),%d1
8020 mov.l %d1,SGN(%a6)
8023 mov.l %d1,X(%a6) # Y = 2|X|
8024 and.l &0x80000000,SGN(%a6)
8025 mov.l SGN(%a6),%d1
8026 fmov.x X(%a6),%fp0 # Y = 2|X|
8035 mov.l SGN(%a6),%d1
8042 mov.l SGN(%a6),%d1
8054 fmov.x X(%a6),%fp0 # last inst - possible exception set
8059 mov.l X(%a6),%d1
8330 mov.l &0x00000000,ADJK(%a6)
8339 mov.l (%a0),X(%a6)
8340 mov.l 4(%a0),X+4(%a6)
8341 mov.l 8(%a0),X+8(%a6)
8367 add.l ADJK(%a6),%d1 # ADJUST K, ORIGINAL INPUT MAY BE DENORM.
8372 mov.l &0x3FFF0000,X(%a6) # X IS NOW Y, I.E. 2^(-K)*X
8373 mov.l XFRAC(%a6),FFRAC(%a6)
8374 and.l &0xFE000000,FFRAC(%a6) # FIRST 7 BITS OF Y
8375 or.l &0x01000000,FFRAC(%a6) # GET F: ATTACH A 1 AT THE EIGHTH BIT
8376 mov.l FFRAC(%a6),%d1 # READY TO GET ADDRESS OF 1/F
8383 fmov.x X(%a6),%fp0
8384 mov.l &0x3fff0000,F(%a6)
8385 clr.l F+8(%a6)
8386 fsub.x F(%a6),%fp0 # Y-F
8397 fmov.x %fp1,KLOG2(%a6) # PUT K*LOG2 IN MEMORY, FREE FP1
8400 #--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS
8401 #--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
8406 fmul.d LOGA6(%pc),%fp1 # V*A6
8409 fadd.d LOGA4(%pc),%fp1 # A4+V*A6
8412 fmul.x %fp3,%fp1 # V*(A4+V*A6)
8415 fadd.d LOGA2(%pc),%fp1 # A2+V*(A4+V*A6)
8418 fmul.x %fp3,%fp1 # V*(A2+V*(A4+V*A6))
8422 fmul.x %fp0,%fp1 # U*V*(A2+V*(A4+V*A6))
8425 fadd.x (%a0),%fp1 # LOG(F)+U*V*(A2+V*(A4+V*A6))
8430 fadd.x KLOG2(%a6),%fp0 # FINAL ADD
8460 fmov.x %fp1,SAVEU(%a6) # STORE U IN MEMORY, FREE FP1
8478 fmul.x SAVEU(%a6),%fp0 # FP0 IS U*V
8486 fadd.x SAVEU(%a6),%fp0
8497 mov.l &-100,ADJK(%a6) # INPUT = 2^(ADJK) * FP0
8522 mov.l %d3,X(%a6)
8523 mov.l %d4,XFRAC(%a6)
8524 mov.l %d5,XFRAC+4(%a6)
8526 mov.l %d2,ADJK(%a6)
8527 fmov.x X(%a6),%fp0
8529 lea X(%a6),%a0
8544 mov.l %d3,X(%a6)
8545 mov.l %d4,XFRAC(%a6)
8546 mov.l %d5,XFRAC+4(%a6)
8548 mov.l %d2,ADJK(%a6)
8549 fmov.x X(%a6),%fp0
8551 lea X(%a6),%a0
8568 mov.l &0x00000000,ADJK(%a6)
8571 fmov.x %fp0,X(%a6)
8572 mov.w XFRAC(%a6),XDCARE(%a6)
8573 mov.l X(%a6),%d1
8609 mov.l XFRAC(%a6),FFRAC(%a6)
8610 and.l &0xFE000000,FFRAC(%a6)
8611 or.l &0x01000000,FFRAC(%a6) # F OBTAINED
8617 mov.l &0x3fff0000,F(%a6)
8618 clr.l F+8(%a6)
8619 fsub.x F(%a6),%fp0 # 2-F
8620 mov.l FFRAC(%a6),%d1
8635 mov.l &0x3fff0000,F(%a6)
8636 clr.l F+8(%a6)
8637 fsub.x F(%a6),%fp0 # 1-F
8638 mov.l FFRAC(%a6),%d1
9105 fmov.x %fp0,X(%a6)
9122 fmov.l %fp1,INT(%a6) # N = ROUND-TO-INT(64 X)
9125 fmov.l INT(%a6),%fp1 # N --> FLOATING FMT
9126 mov.l INT(%a6),%d1
9145 mov.l (%a1)+,FACT1(%a6)
9146 mov.l (%a1)+,FACT1HI(%a6)
9147 mov.l (%a1)+,FACT1LOW(%a6)
9148 mov.w (%a1)+,FACT2(%a6)
9152 mov.w (%a1)+,FACT2HI(%a6)
9153 clr.w FACT2HI+2(%a6)
9154 clr.l FACT2LOW(%a6)
9155 add.w %d1,FACT1(%a6)
9157 add.w %d1,FACT2(%a6)
9175 mov.l X(%a6),%d1
9202 fmov.x %fp0,X(%a6)
9219 fmov.l %fp1,INT(%a6) # N=INT(X*64*LOG10/LOG2)
9222 fmov.l INT(%a6),%fp1 # N --> FLOATING FMT
9223 mov.l INT(%a6),%d1
9243 mov.l (%a1)+,FACT1(%a6)
9247 mov.l (%a1)+,FACT1HI(%a6)
9248 mov.l (%a1)+,FACT1LOW(%a6)
9250 mov.w (%a1)+,FACT2(%a6)
9254 mov.w (%a1)+,FACT2HI(%a6)
9255 clr.w FACT2HI+2(%a6)
9256 clr.l FACT2LOW(%a6)
9259 add.w %d1,FACT1(%a6)
9260 add.w %d1,FACT2(%a6)
9295 fmul.x FACT1(%a6),%fp0
9296 fadd.x FACT2(%a6),%fp0
9297 fadd.x FACT1(%a6),%fp0
9300 mov.w %d2,ADJFACT(%a6) # INSERT EXPONENT
9302 mov.l &0x80000000,ADJFACT+4(%a6)
9303 clr.l ADJFACT+8(%a6)
9305 fmul.x ADJFACT(%a6),%fp0 # FINAL ADJUSTMENT
9460 ori.l &inx2a_mask,USER_FPSR(%a6) # set INEX2/AINEX
9479 mov.w 0x0(%a0,%d1.w),FP_SCR1_EX(%a6) # load first word
9480 mov.l 0x4(%a0,%d1.w),FP_SCR1_HI(%a6) # load second word
9481 mov.l 0x8(%a0,%d1.w),FP_SCR1_LO(%a6) # load third word
9484 lea FP_SCR1(%a6),%a0 # pass ptr to answer
9593 smi.b SIGN(%a6) # use SIGN to hold dst sign
9621 mov.w DST_EX(%a1),FP_SCR0_EX(%a6) # make a copy
9622 mov.l DST_HI(%a1),FP_SCR0_HI(%a6)
9623 mov.l DST_LO(%a1),FP_SCR0_LO(%a6)
9625 lea FP_SCR0(%a6),%a0 # pass ptr to DENORM
9630 fmovm.x FP_SCR0(%a6),&0x80 # load normalized DENORM
9788 clr.b FPSR_QBYTE(%a6)
9790 clr.b Mod_Flag(%a6)
9795 clr.b FPSR_QBYTE(%a6)
9797 mov.b &0x1,Mod_Flag(%a6)
9803 mov.w %d3,SignY(%a6)
9848 mov.w %d0,SignX(%a6)
9849 mov.w SignY(%a6),%d1
9852 mov.w %d1,SignQ(%a6) # sign(Q) obtained
9893 mov.l %d3,L_SCR1(%a6) # save biased exp(Y)
9957 mov.l L_SCR1(%a6),%d0 # new biased expo of R
9990 mov.w %d0,R(%a6)
9991 mov.l %d1,R_Hi(%a6)
9992 mov.l %d2,R_Lo(%a6)
9993 mov.l L_SCR1(%a6),%d6
9994 mov.w %d6,Y(%a6)
9995 mov.l %d4,Y_Hi(%a6)
9996 mov.l %d5,Y_Lo(%a6)
9997 fmov.x R(%a6),%fp0 # no exception
9998 mov.b &1,Sc_Flag(%a6)
10001 mov.l %d1,R_Hi(%a6)
10002 mov.l %d2,R_Lo(%a6)
10004 a6)
10005 mov.l L_SCR1(%a6),%d6
10007 mov.l %d6,L_SCR1(%a6)
10008 fmov.x R(%a6),%fp0
10009 mov.w %d6,Y(%a6)
10010 mov.l %d4,Y_Hi(%a6)
10011 mov.l %d5,Y_Lo(%a6)
10012 clr.b Sc_Flag(%a6)
10016 tst.b Mod_Flag(%a6)
10019 mov.l L_SCR1(%a6),%d6 # new biased expo(Y)
10036 fsub.x Y(%a6),%fp0 # no exceptions
10042 mov.w SignX(%a6),%d6
10050 mov.w SignQ(%a6),%d6 # D6 is sign(Q)
10060 mov.b %d3,FPSR_QBYTE(%a6) # put Q in fpsr
10067 tst.b Sc_Flag(%a6)
10098 clr.b Sc_Flag(%a6)
10110 mov.w SignX(%a6),%d6
10112 mov.w %d6,SignX(%a6)
10147 ori.l &dzinf_mask,USER_FPSR(%a6) # set I/DZ/ADZ
10153 ori.l &dzinf_mask+neg_mask,USER_FPSR(%a6) # set N/I/DZ/ADZ
10163 ori.l &opnan_mask,USER_FPSR(%a6) # set NaN/OPERR/AIOP
10179 ori.l &unfl_mask,USER_FPSR(%a6) # set UNFL
10184 ori.l &unfinx_mask,USER_FPSR(%a6) # set UNFL/INEX2/AUNFL/AINEX
10196 bset &neg_bit,FPSR_CC(%a6) # yes; set 'N' ccode bit
10209 mov.b FPCR_ENABLE(%a6),%d0
10221 mov.w LOCAL_EX(%a1),FP_SCR0_EX(%a6)
10222 mov.l LOCAL_HI(%a1),FP_SCR0_HI(%a6)
10223 mov.l LOCAL_LO(%a1),FP_SCR0_LO(%a6)
10225 lea FP_SCR0(%a6),%a0
10228 andi.w &0x8000,FP_SCR0_EX(%a6) # keep old sign
10229 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent
10231 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
10247 ori.l &unfinx_mask,USER_FPSR(%a6) # set UNFL/INEX2/AUNFL/AINEX
10260 ori.l &unfinx_mask,USER_FPSR(%a6) # set UNFL/INEX2/AUNFL/AINEX
10285 ori.l &ovfl_inx_mask,USER_FPSR(%a6) # set OVFL/AOVFL/AINEX
10297 mov.w LOCAL_EX(%a0),FP_SCR0_EX(%a6)
10298 mov.l LOCAL_HI(%a0),FP_SCR0_HI(%a6)
10299 mov.l LOCAL_LO(%a0),FP_SCR0_LO(%a6)
10300 lea FP_SCR0(%a6),%a0 # pass ptr to FP_SCR0
10319 ori.l &inex2_mask,USER_FPSR(%a6) # set INEX2
10324 ori.l &ovfinx_mask,USER_FPSR(%a6) # set OVFL/INEX2/AOVFL/AINEX
10330 mov.b %d0,FPSR_CC(%a6) # insert new ccodes
10339 ori.l &ovfinx_mask,USER_FPSR(%a6) # set OVFL/INEX2/AOVFL/AINEX
10343 mov.b %d0,FPSR_CC(%a6) # insert new ccodes
10377 ori.w &inx2a_mask,2+USER_FPSR(%a6) # set INEX2/AINEX
10382 ori.l &inx2a_mask+neg_mask,USER_FPSR(%a6) # set N/INEX2/AINEX
10386 mov.b &z_bmask,FPSR_CC(%a6)
10387 ori.w &inx2a_mask,2+USER_FPSR(%a6) # set INEX2/AINEX
10393 ori.w &inx2a_mask,FPSR_EXCEPT(%a6)
10409 or.l %d0,USER_FPSR(%a6)
10425 ori.l &unfinx_mask,USER_FPSR(%a6)
10436 mov.b (tbl_unf_cc.b,%pc,%d0.w*1),FPSR_CC(%a6) # insert ccode bits
10501 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
10508 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set 'N','Z' ccode bits
10534 mov.b &inf_bmask,FPSR_CC(%a6) # set 'INF' ccode bit
10543 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
10602 clr.b FPSR_CC(%a6)
10611 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
10658 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6)
10662 mov.b &z_bmask,FPSR_CC(%a6)
10709 mov.b 1+EXC_CMDREG(%a6),%d0
10725 fmovm.x &0x40,EXC_FP0(%a6)
10728 fmovm.x &0x40,EXC_FP1(%a6)
10754 mov.b DTAG(%a6),%d1
10768 mov.b DTAG(%a6),%d1
10782 mov.b DTAG(%a6),%d1
10800 mov.b %d1,FPSR_QBYTE(%a6)
10807 clr.b FPSR_QBYTE(%a6)
10813 mov.b %d1,FPSR_QBYTE(%a6)
10814 cmpi.b DTAG(%a6),&DENORM
10827 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode
10835 mov.b DTAG(%a6),%d1
10849 mov.b DTAG(%a6),%d1
10863 mov.b DTAG(%a6),%d1
10880 mov.b DTAG(%a6),%d1
10894 mov.b DTAG(%a6),%d1
10908 mov.b DTAG(%a6),%d1
10923 mov.b DTAG(%a6),%d1
10935 mov.b DTAG(%a6),%d1
10943 ori.l &snaniop_mask,USER_FPSR(%a6) # set NAN/SNAN/AIOP
10953 or.l %d0,USER_FPSR(%a6) # store status
10965 mov.b &nan_bmask,FPSR_CC(%a6)
10968 mov.b &neg_bmask+nan_bmask,FPSR_CC(%a6)
10978 or.l %d0,USER_FPSR(%a6) # store status
10990 mov.b &nan_bmask,FPSR_CC(%a6)
10993 mov.b &neg_bmask+nan_bmask,FPSR_CC(%a6)
11007 mov.b STAG(%a6),%d1
11021 mov.b STAG(%a6),%d1
11035 mov.b STAG(%a6),%d1
11049 mov.b STAG(%a6),%d1
11063 mov.b STAG(%a6),%d1
11077 mov.b STAG(%a6),%d1
11091 mov.b STAG(%a6),%d1
11105 mov.b STAG(%a6),%d1
11119 mov.b STAG(%a6),%d1
11133 mov.b STAG(%a6),%d1
11147 mov.b STAG(%a6),%d1
11161 mov.b STAG(%a6),%d1
11175 mov.b STAG(%a6),%d1
11189 mov.b STAG(%a6),%d1
11203 mov.b STAG(%a6),%d1
11217 mov.b STAG(%a6),%d1
11231 mov.b STAG(%a6),%d1
11245 mov.b STAG(%a6),%d1
11259 mov.b STAG(%a6),%d1
11273 mov.b STAG(%a6),%d1
11287 mov.b STAG(%a6),%d1
11301 mov.b STAG(%a6),%d1
11315 mov.b STAG(%a6),%d1
11329 mov.b STAG(%a6),%d1
11374 mov.b &NORM,STAG(%a6)
11377 mov.b &NORM,DTAG(%a6)
11387 fmovm.x &0x80,FP_DST(%a6) # dst op is in fp0
11390 lea FP_DST(%a6),%a1 # pass: ptr to dst op
11407 mov.b &DENORM,STAG(%a6)
11588 mov.l %d0,L_SCR3(%a6) # store rnd info
11591 mov.b DTAG(%a6),%d1
11593 or.b STAG(%a6),%d1 # combine src tags
11597 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
11598 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
11599 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
11601 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
11602 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
11603 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
11612 mov.w 2+L_SCR3(%a6),%d1 # fetch precision
11632 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11634 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11637 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11642 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11645 fmovm.x &0x80,FP_SCR0(%a6) # store out result
11647 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
11653 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11655 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
11672 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11674 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11677 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11682 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11686 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
11688 mov.b FPCR_ENABLE(%a6),%d1
11694 btst &neg_bit,FPSR_CC(%a6) # is result negative?
11696 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode
11698 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
11709 mov.l L_SCR3(%a6),%d1
11714 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
11717 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
11725 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11727 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
11731 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11733 mov.l L_SCR3(%a6),%d1
11737 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11750 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
11752 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11755 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11760 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11783 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
11788 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11793 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11798 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11800 mov.b FPCR_ENABLE(%a6),%d1
11805 fmovm.x &0x80,FP_SCR0(%a6) # store out result
11807 lea FP_SCR0(%a6),%a0 # pass: result addr
11808 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
11810 or.b %d0,FPSR_CC(%a6) # unf_res2 may have set 'Z'
11811 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
11818 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
11820 mov.l L_SCR3(%a6),%d1
11826 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11831 fmul.x FP_SCR0(%a6),%fp1 # execute multiply
11835 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
11837 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
11845 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
11847 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
11851 mov.l L_SCR3(%a6),%d1
11861 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
11863 fmov.l L_SCR3(%a6),%fpcr # set FPCR
11866 fmul.x FP_SCR0(%a6),%fp0 # execute multiply
11871 or.l %d1,USER_FPSR(%a6) # save INEX2,N
11885 fmovm.x FP_SCR1(%a6),&0x40 # load dst operand
11887 mov.l L_SCR3(%a6),%d1
11894 fmul.x FP_SCR0(%a6),%fp1 # execute multiply
11985 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N
11989 mov.b &z_bmask,FPSR_CC(%a6) # set Z
12010 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N
12014 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
12073 mov.l %d0,L_SCR3(%a6) # store rnd info
12075 mov.b STAG(%a6),%d1 # fetch src optype tag
12092 bset &neg_bit,FPSR_CC(%a6) # yes, so set 'N' ccode bit
12105 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12108 bset &neg_bit,FPSR_CC(%a6) # yes, so set 'N' ccode bit
12111 btst &unfl_bit,FPCR_ENABLE(%a6) # is UNFL enabled?
12121 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12122 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12123 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12124 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
12128 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
12132 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
12133 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12147 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12148 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12149 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12163 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12165 fmov.x FP_SCR0(%a6),%fp0 # perform move
12170 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12174 fmovm.x &0x80,FP_SCR0(%a6) # store out result
12175 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
12181 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent
12183 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
12190 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12191 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12192 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12206 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12208 tst.b FP_SCR0_EX(%a6) # is operand negative?
12210 bset &neg_bit,FPSR_CC(%a6) # set 'N' ccode bit
12214 mov.b FPCR_ENABLE(%a6),%d1
12219 lea FP_SCR0(%a6),%a0 # pass: result addr
12220 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
12222 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
12223 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
12231 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
12232 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
12233 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
12243 mov.w %d2,FP_SCR1_EX(%a6) # insert new exponent
12244 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
12253 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12255 fmov.x FP_SCR0(%a6),%fp0 # perform move
12260 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12263 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
12265 mov.b FPCR_ENABLE(%a6),%d1
12274 btst &neg_bit,FPSR_CC(%a6) # is result negative?
12276 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
12278 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
12289 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
12297 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
12299 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12307 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12309 fmov.x FP_SCR0(%a6),%fp0 # perform the move
12314 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12344 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes
12406 mov.l %d0,L_SCR3(%a6) # store rnd info
12409 mov.b DTAG(%a6),%d1
12411 or.b STAG(%a6),%d1 # combine src tags
12419 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
12420 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
12421 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
12423 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12424 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12425 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12435 mov.w 2+L_SCR3(%a6),%d1 # fetch precision
12446 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
12448 fmov.l L_SCR3(%a6),%fpcr # save FPCR
12451 fdiv.x FP_SCR0(%a6),%fp0 # perform divide
12456 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12459 fmovm.x &0x80,FP_SCR0(%a6) # store result on stack
12461 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
12467 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
12469 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
12484 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
12486 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12489 fdiv.x FP_SCR0(%a6),%fp0 # execute divide
12494 or.l %d0,USER_FPSR(%a6) # save INEX,N
12506 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
12508 mov.b FPCR_ENABLE(%a6),%d1
12513 btst &neg_bit,FPSR_CC(%a6) # is result negative?
12515 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
12517 or.b %d0,FPSR_CC(%a6) # set INF if applicable
12522 mov.l L_SCR3(%a6),%d1
12527 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
12530 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
12538 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
12540 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12544 fmovm.x FP_SCR1(%a6),&0x80 # load dst operand
12546 mov.l L_SCR3(%a6),%d1
12550 fdiv.x FP_SCR0(%a6),%fp0 # execute divide
12556 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12558 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
12563 fdiv.x FP_SCR0(%a6),%fp0 # execute divide
12568 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12570 mov.b FPCR_ENABLE(%a6),%d1
12575 fmovm.x &0x80,FP_SCR0(%a6) # store out result
12577 lea FP_SCR0(%a6),%a0 # pass: result addr
12578 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
12580 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set
12581 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
12588 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
12590 mov.l L_SCR3(%a6),%d1
12594 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12599 fdiv.x FP_SCR0(%a6),%fp1 # execute divide
12603 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
12605 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
12613 mov.w %d1,FP_SCR0_EX(%a6) # insert new exp
12615 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12619 mov.l L_SCR3(%a6),%d1
12629 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
12631 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12634 fdiv.x FP_SCR0(%a6),%fp0 # execute divide
12639 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12653 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
12655 mov.l L_SCR3(%a6),%d1
12662 fdiv.x FP_SCR0(%a6),%fp1 # execute divide
12749 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/N
12753 mov.b &z_bmask,FPSR_CC(%a6) # set Z
12763 ori.w &dz_mask+adz_mask,2+USER_FPSR(%a6) # no; set DZ/ADZ
12769 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/N
12773 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
12792 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set INF/NEG
12798 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
12847 mov.l %d0,L_SCR3(%a6) # store rnd info
12848 mov.b STAG(%a6),%d1
12863 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12864 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12868 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
12870 mov.w %d0,FP_SCR0_EX(%a6)
12871 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
12882 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12884 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12885 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12889 mov.b &neg_bmask,FPSR_CC(%a6) # yes, set 'N' ccode bit
12891 mov.w %d0,FP_SCR0_EX(%a6)
12892 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
12894 btst &unfl_bit,FPCR_ENABLE(%a6) # is UNFL enabled?
12904 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
12908 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
12912 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
12913 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
12927 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12928 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12929 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12943 fmov.l L_SCR3(%a6),%fpcr # set FPCR
12945 fneg.x FP_SCR0(%a6),%fp0 # perform negation
12950 or.l %d1,USER_FPSR(%a6) # save INEX2,N
12954 fmovm.x &0x80,FP_SCR0(%a6) # store out result
12955 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
12961 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent
12963 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
12970 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
12971 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
12972 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
12986 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
12988 eori.b &0x80,FP_SCR0_EX(%a6) # negate sign
12990 bset &neg_bit,FPSR_CC(%a6) # set 'N' ccode bit
12994 mov.b FPCR_ENABLE(%a6),%d1
12999 lea FP_SCR0(%a6),%a0 # pass: result addr
13000 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
13002 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
13003 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
13011 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
13012 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
13013 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
13023 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
13024 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
13033 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13035 fneg.x FP_SCR0(%a6),%fp0 # perform negation
13040 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13043 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
13045 mov.b FPCR_ENABLE(%a6),%d1
13054 btst &neg_bit,FPSR_CC(%a6) # is result negative?
13056 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
13058 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
13069 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
13077 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
13078 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
13087 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13089 fneg.x FP_SCR0(%a6),%fp0 # perform negation
13094 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13124 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes
13148 mov.b STAG(%a6),%d1
13159 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13183 mov.b &neg_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13193 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13196 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits
13206 mov.b &z_bmask,FPSR_CC(%a6) # set 'N' ccode bit
13209 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13240 mov.b STAG(%a6),%d1
13256 or.l %d0,USER_FPSR(%a6) # set exception bits
13284 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp
13285 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM
13286 lea FP_SCR0(%a6),%a0
13297 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13301 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13312 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13315 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
13346 mov.b STAG(%a6),%d1
13358 or.l %d0,USER_FPSR(%a6) # set exception bits
13386 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6) # copy sign, zero exp
13387 mov.b &0x80,FP_SCR0_HI(%a6) # force DENORM ==> small NORM
13388 lea FP_SCR0(%a6),%a0
13399 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13403 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
13414 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13417 mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'N','I' ccode bits
13470 mov.l %d0,L_SCR3(%a6) # store rnd info
13471 mov.b STAG(%a6),%d1
13486 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13487 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13490 mov.w %d1,FP_SCR0_EX(%a6) # insert exponent
13491 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
13502 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
13504 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13505 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13508 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent
13510 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
13512 btst &unfl_bit,FPCR_ENABLE(%a6) # is UNFL enabled?
13522 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
13526 mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
13530 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
13531 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
13545 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13546 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13547 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13561 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13563 fabs.x FP_SCR0(%a6),%fp0 # perform absolute
13568 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13572 fmovm.x &0x80,FP_SCR0(%a6) # store out result
13573 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
13579 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent
13581 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
13588 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13589 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13590 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13604 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
13606 bclr &0x7,FP_SCR0_EX(%a6) # force absolute value
13609 mov.b FPCR_ENABLE(%a6),%d1
13614 lea FP_SCR0(%a6),%a0 # pass: result addr
13615 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
13617 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
13618 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
13626 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
13627 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
13628 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
13638 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
13639 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
13648 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13650 fabs.x FP_SCR0(%a6),%fp0 # perform absolute
13655 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13658 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
13660 mov.b FPCR_ENABLE(%a6),%d1
13669 btst &neg_bit,FPSR_CC(%a6) # is result negative?
13671 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
13673 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
13684 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
13692 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
13693 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
13702 fmov.l L_SCR3(%a6),%fpcr # set FPCR
13704 fabs.x FP_SCR0(%a6),%fp0 # perform absolute
13709 or.l %d1,USER_FPSR(%a6) # save INEX2,N
13736 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13739 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
13768 mov.b DTAG(%a6),%d1
13770 or.b STAG(%a6),%d1
13783 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set)
13854 andi.b &0xf7,FPSR_CC(%a6)
13858 andi.b &0xf7,FPSR_CC(%a6)
13874 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13877 mov.l %d0,FP_SCR0_HI(%a6)
13878 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13879 lea FP_SCR0(%a6),%a0
13883 mov.l DST_EX(%a1),FP_SCR0_EX(%a6)
13886 mov.l %d0,FP_SCR0_HI(%a6)
13887 mov.l DST_LO(%a1),FP_SCR0_LO(%a6)
13888 lea FP_SCR0(%a6),%a1
13892 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
13893 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13896 mov.l %d0,FP_SCR1_HI(%a6)
13899 mov.l %d0,FP_SCR0_HI(%a6)
13900 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
13901 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
13902 lea FP_SCR1(%a6),%a1
13903 lea FP_SCR0(%a6),%a0
13917 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13931 mov.b &neg_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
13969 mov.l %d0,L_SCR3(%a6) # store rnd info
13972 mov.b DTAG(%a6),%d1
13974 or.b STAG(%a6),%d1
13979 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
13980 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
13981 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
13983 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
13984 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
13985 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
14003 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14005 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14008 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14013 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14016 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14018 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
14024 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14026 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
14030 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14032 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14035 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14040 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14045 or.l &ovfl_inx_mask, USER_FPSR(%a6) # set ovfl/aovfl/ainex
14047 mov.b FPCR_ENABLE(%a6),%d1
14052 btst &neg_bit,FPSR_CC(%a6) # is result negative?
14054 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14057 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
14062 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
14065 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14073 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14075 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14079 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14081 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14084 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14089 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14099 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
14101 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14106 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14111 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14113 mov.b FPCR_ENABLE(%a6),%d1
14118 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14120 lea FP_SCR0(%a6),%a0 # pass: result addr
14121 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
14123 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14124 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
14131 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
14133 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14136 fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
14140 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
14142 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14150 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14152 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14156 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14158 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14161 fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
14166 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14180 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
14182 mov.l L_SCR3(%a6),%d1
14189 fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
14310 mov.l %d0,L_SCR3(%a6) # store rnd info
14313 mov.b DTAG(%a6),%d1
14315 or.b STAG(%a6),%d1 # combine src tags
14323 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
14324 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
14325 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
14327 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
14328 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
14329 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
14339 mov.w 2+L_SCR3(%a6),%d1 # fetch precision,mode
14350 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14352 fmov.l L_SCR3(%a6),%fpcr # save FPCR
14355 fsgldiv.x FP_SCR0(%a6),%fp0 # perform sgl divide
14360 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14363 fmovm.x &0x80,FP_SCR0(%a6) # store result on stack
14365 mov.w FP_SCR0_EX(%a6),%d1 # load {sgn,exp}
14371 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14373 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
14377 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14379 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14382 fsgldiv.x FP_SCR0(%a6),%fp0 # execute divide
14387 or.l %d1,USER_FPSR(%a6) # save INEX,N
14398 or.w &ovfl_inx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex
14400 mov.b FPCR_ENABLE(%a6),%d1
14405 btst &neg_bit,FPSR_CC(%a6) # is result negative
14407 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14410 or.b %d0,FPSR_CC(%a6) # set INF if applicable
14415 fmovm.x &0x80,FP_SCR0(%a6) # move result to stack
14418 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14426 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14428 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14432 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
14434 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14439 fsgldiv.x FP_SCR0(%a6),%fp0 # execute sgl divide
14444 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14446 mov.b FPCR_ENABLE(%a6),%d1
14451 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14453 lea FP_SCR0(%a6),%a0 # pass: result addr
14454 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
14456 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14457 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
14464 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
14466 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14469 fsgldiv.x FP_SCR0(%a6),%fp1 # execute sgl divide
14473 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
14475 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14483 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14485 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14492 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14494 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14497 fsgldiv.x FP_SCR0(%a6),%fp0 # execute sgl divide
14502 or.l %d1,USER_FPSR(%a6) # save INEX2,N
14516 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into %fp1
14524 fsgldiv.x FP_SCR0(%a6),%fp1 # execute sgl divide
14657 mov.l %d0,L_SCR3(%a6) # store rnd info
14660 mov.b DTAG(%a6),%d1
14662 or.b STAG(%a6),%d1 # combine src tags
14673 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14676 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14678 fadd.x FP_SCR0(%a6),%fp0 # execute add
14683 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
14691 mov.w 2+L_SCR3(%a6),%d1
14731 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
14733 mov.b FPCR_ENABLE(%a6),%d1
14739 btst &neg_bit,FPSR_CC(%a6) # is result negative?
14741 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
14743 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
14749 mov.b L_SCR3(%a6),%d1
14765 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14767 mov.l L_SCR3(%a6),%d1
14771 fadd.x FP_SCR0(%a6),%fp0 # execute add
14780 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
14784 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
14789 fadd.x FP_SCR0(%a6),%fp0 # execute add
14794 or.l %d1,USER_FPSR(%a6) # save INEX,N
14796 mov.b FPCR_ENABLE(%a6),%d1
14801 fmovm.x &0x80,FP_SCR0(%a6) # store out result
14803 lea FP_SCR0(%a6),%a0 # pass: result addr
14804 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
14806 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set
14807 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
14812 fmovm.x FP_SCR1(%a6),&0x40 # load dst op
14814 mov.l L_SCR3(%a6),%d1
14818 fmov.l L_SCR3(%a6),%fpcr # set FPCR
14823 fadd.x FP_SCR0(%a6),%fp1 # execute multiply
14827 fmovm.x &0x40,FP_SCR0(%a6) # save result to stack
14828 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
14836 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
14837 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
14841 mov.l L_SCR3(%a6),%d1
14853 mov.l L_SCR3(%a6),%d1
14864 btst &inex2_bit,FPSR_EXCEPT(%a6) # is INEX2 set?
14877 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
14879 mov.l L_SCR3(%a6),%d1
14885 fadd.x FP_SCR0(%a6),%fp1 # execute add
14980 mov.b &z_bmask,FPSR_CC(%a6) # set Z
14989 mov.b 3+L_SCR3(%a6),%d1
14994 mov.b &z_bmask,FPSR_CC(%a6) # set Z
14999 mov.b &neg_bmask+z_bmask,FPSR_CC(%a6) # set NEG/Z
15007 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15008 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15009 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15011 clr.w FP_SCR1_EX(%a6)
15012 clr.l FP_SCR1_HI(%a6)
15013 clr.l FP_SCR1_LO(%a6)
15017 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
15018 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15019 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15021 clr.w FP_SCR0_EX(%a6)
15022 clr.l FP_SCR0_HI(%a6)
15023 clr.l FP_SCR0_LO(%a6)
15046 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15056 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15060 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
15110 mov.l %d0,L_SCR3(%a6) # store rnd info
15113 mov.b DTAG(%a6),%d1
15115 or.b STAG(%a6),%d1 # combine src tags
15126 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15129 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15131 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15136 or.l %d1,USER_FPSR(%a6) # save exc and ccode bits
15144 mov.w 2+L_SCR3(%a6),%d1
15184 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
15186 mov.b FPCR_ENABLE(%a6),%d1
15192 btst &neg_bit,FPSR_CC(%a6) # is result negative?
15194 mov.l L_SCR3(%a6),%d0 # pass prec:rnd
15196 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
15202 mov.b L_SCR3(%a6),%d1
15218 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15220 mov.l L_SCR3(%a6),%d1
15224 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15233 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
15237 fmovm.x FP_SCR1(%a6),&0x80 # load dst op
15242 fsub.x FP_SCR0(%a6),%fp0 # execute subtract
15247 or.l %d1,USER_FPSR(%a6)
15249 mov.b FPCR_ENABLE(%a6),%d1
15254 fmovm.x &0x80,FP_SCR0(%a6) # store out result
15256 lea FP_SCR0(%a6),%a0 # pass: result addr
15257 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
15259 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set
15260 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
15265 fmovm.x FP_SCR1(%a6),&0x40
15267 mov.l L_SCR3(%a6),%d1
15271 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15276 fsub.x FP_SCR0(%a6),%fp1 # execute subtract
15280 fmovm.x &0x40,FP_SCR0(%a6) # store result to stack
15281 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
15289 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
15290 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
15294 mov.l L_SCR3(%a6),%d1
15306 mov.l L_SCR3(%a6),%d1
15317 btst &inex2_bit,FPSR_EXCEPT(%a6) # is INEX2 set?
15330 fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
15332 mov.l L_SCR3(%a6),%d1
15338 fsub.x FP_SCR0(%a6),%fp1 # execute subtract
15432 mov.b &z_bmask,FPSR_CC(%a6) # set Z
15441 mov.b 3+L_SCR3(%a6),%d1
15446 mov.b &z_bmask,FPSR_CC(%a6) # set Z
15451 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set Z/NEG
15459 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15460 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15461 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15463 clr.w FP_SCR1_EX(%a6)
15464 clr.l FP_SCR1_HI(%a6)
15465 clr.l FP_SCR1_LO(%a6)
15469 mov.w DST_EX(%a1),FP_SCR1_EX(%a6)
15470 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15471 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15473 clr.w FP_SCR0_EX(%a6)
15474 clr.l FP_SCR0_HI(%a6)
15475 clr.l FP_SCR0_LO(%a6)
15495 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15502 mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
15506 mov.b &inf_bmask,FPSR_CC(%a6) # set INF
15555 mov.l %d0,L_SCR3(%a6) # store rnd info
15557 mov.b STAG(%a6),%d1
15570 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15576 or.l %d1,USER_FPSR(%a6) # set N,INEX
15587 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15588 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15589 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15606 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15607 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15608 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15624 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15626 fsqrt.x FP_SCR0(%a6),%fp0 # perform absolute
15631 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15635 fmovm.x &0x80,FP_SCR0(%a6) # store out result
15636 mov.w FP_SCR0_EX(%a6),%d1 # load sgn,exp
15642 mov.w %d2,FP_SCR0_EX(%a6) # insert new exponent
15644 fmovm.x FP_SCR0(%a6),&0x80 # return result in fp0
15651 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
15652 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15653 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15669 btst &0x0,1+FP_SCR0_EX(%a6) # is exponent 0x3fff?
15676 bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
15681 fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
15686 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15689 mov.b FPCR_ENABLE(%a6),%d1
15694 fmovm.x &0x80,FP_SCR0(%a6) # store out result
15696 lea FP_SCR0(%a6),%a0 # pass: result addr
15697 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
15699 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
15700 fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
15708 mov.l FP_SCR0_HI(%a6),FP_SCR1_HI(%a6)
15709 mov.l FP_SCR0_LO(%a6),FP_SCR1_LO(%a6)
15710 mov.w FP_SCR0_EX(%a6),%d1 # load current exponent
15720 mov.w %d1,FP_SCR1_EX(%a6) # insert new exp
15721 fmovm.x FP_SCR1(%a6),&0x40 # return EXOP in fp1
15730 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15732 fsqrt.x FP_SCR0(%a6),%fp0 # perform square root
15737 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15740 or.l &ovfl_inx_mask,USER_FPSR(%a6) # set ovfl/aovfl/ainex
15742 mov.b FPCR_ENABLE(%a6),%d1
15751 btst &neg_bit,FPSR_CC(%a6) # is result negative?
15753 mov.l L_SCR3(%a6),%d0 # pass: prec,mode
15755 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable
15766 mov.w FP_SCR0_EX(%a6),%d1 # fetch {sgn,exp}
15774 mov.w %d1,FP_SCR0_EX(%a6) # insert new exponent
15775 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
15783 btst &0x0,1+FP_SCR0_EX(%a6) # is exponent 0x3fff?
15787 fmov.l L_SCR3(%a6),%fpcr # set FPCR
15789 fsqrt.x FP_SCR0(%a6),%fp0 # perform absolute
15794 or.l %d1,USER_FPSR(%a6) # save INEX2,N
15830 mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
15834 mov.b &z_bmask+neg_bmask,FPSR_CC(%a6) # set 'Z','N' ccode bits
15842 mov.b &inf_bmask,FPSR_CC(%a6) # set 'I' ccode bit
15856 # FP_SRC(a6) = fp op1(src) #
15857 # FP_DST(a6) = fp op2(dst) #
15860 # FP_SRC(a6) = fp op1 scaled(src) #
15861 # FP_DST(a6) = fp op2 scaled(dst) #
15877 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
15878 mov.l DST_HI(%a1),FP_SCR1_HI(%a6)
15879 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
15880 mov.l DST_LO(%a1),FP_SCR1_LO(%a6)
15883 mov.w %d0,FP_SCR0_EX(%a6)
15884 mov.w %d1,FP_SCR1_EX(%a6)
15888 mov.w %d0,L_SCR1(%a6) # store src exponent
15889 mov.w %d1,2+L_SCR1(%a6) # store dst exponent
15899 cmpi.b STAG(%a6),&DENORM # is dst denormalized?
15902 lea FP_SCR0(%a6),%a0
15905 mov.w %d0,L_SCR1(%a6) # inset new exp
15908 mov.w 2+L_SCR1(%a6),%d0
15911 cmp.w %d0,L_SCR1(%a6) # is difference >= len(mantissa)+2?
15914 mov.w L_SCR1(%a6),%d0
15916 mov.w FP_SCR0_EX(%a6),%d1
15919 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent
15925 andi.w &0x8000,FP_SCR0_EX(%a6) # zero src exponent
15926 bset &0x0,1+FP_SCR0_EX(%a6) # set exp = 1
15936 cmpi.b DTAG(%a6),&DENORM # is dst denormalized?
15938 lea FP_SCR1(%a6),%a0
15941 mov.w %d0,2+L_SCR1(%a6) # inset new exp
15944 mov.w L_SCR1(%a6),%d0
15947 cmp.w %d0,2+L_SCR1(%a6) # is difference >= len(mantissa)+2?
15950 mov.w 2+L_SCR1(%a6),%d0
15952 mov.w FP_SCR1_EX(%a6),%d1
15955 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent
15961 andi.w &0x8000,FP_SCR1_EX(%a6) # zero dst exponent
15962 bset &0x0,1+FP_SCR1_EX(%a6) # set exp = 1
15972 # value at FP_SCR0(a6). #
15978 # FP_SCR0(a6) = extended precision operand to be scaled #
15981 # FP_SCR0(a6) = scaled extended precision operand #
15994 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp}
16002 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent
16004 cmpi.b STAG(%a6),&DENORM # is operand normalized?
16014 lea FP_SCR0(%a6),%a0 # pass ptr to src op
16031 # FP_SCR0(a6) = extended precision operand to be scaled #
16034 # FP_SCR0(a6) = scaled extended precision operand #
16048 cmpi.b STAG(%a6),&DENORM # is operand normalized?
16051 mov.w FP_SCR0_EX(%a6),%d1 # extract operand's {sgn,exp}
16054 andi.w &0x8000,FP_SCR0_EX(%a6) # extract operand's sgn
16059 ori.w &0x3fff,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16067 ori.w &0x3ffe,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16075 lea FP_SCR0(%a6),%a0 # pass ptr to src op
16081 ori.w &0x3fff,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16088 ori.w &0x3ffe,FP_SCR0_EX(%a6) # insert new operand's exponent(=0)
16099 # value at FP_SCR1(a6). #
16105 # FP_SCR1(a6) = extended precision operand to be scaled #
16108 # FP_SCR1(a6) = scaled extended precision operand #
16121 mov.w FP_SCR1_EX(%a6),%d1 # extract operand's {sgn,exp}
16129 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent
16131 cmpi.b DTAG(%a6
16140 lea FP_SCR1(%a6),%a0 # pass ptr to dst op
16159 # FP_SRC(a6) = pointer to extended precision src operand #
16160 # FP_DST(a6) = pointer to extended precision dst operand #
16185 cmp.b DTAG(%a6), &SNAN # is the dst an SNAN?
16187 cmp.b DTAG(%a6), &QNAN # is the dst a QNAN?
16190 cmp.b STAG(%a6), &QNAN
16195 bset &0x6, FP_SRC_HI(%a6) # set SNAN bit
16196 or.l &nan_mask+aiop_mask+snan_mask, USER_FPSR(%a6)
16197 lea FP_SRC(%a6), %a0
16202 or.l &nan_mask, USER_FPSR(%a6)
16203 lea FP_SRC(%a6), %a0
16206 or.l &nan_mask+aiop_mask+snan_mask, USER_FPSR(%a6)
16207 bset &0x6, FP_DST_HI(%a6) # set SNAN bit
16208 lea FP_DST(%a6), %a0
16211 lea FP_DST(%a6), %a0
16212 cmp.b STAG(%a6), &SNAN
16214 or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
16216 or.l &nan_mask, USER_FPSR(%a6)
16220 or.l &neg_mask, USER_FPSR(%a6)
16249 or.l &nan_mask+operr_mask+aiop_mask, USER_FPSR(%a6)
16289 mov.l %d0,L_SCR1(%a6) # save displacement
16291 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate
16294 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes
16384 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16386 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16387 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16403 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16405 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16406 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16419 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16421 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16422 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16426 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16428 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16429 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16444 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16446 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16447 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16460 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16462 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16463 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16479 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16481 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16482 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16495 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16497 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16498 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16502 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16504 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16505 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16520 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16522 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16523 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16536 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16538 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16539 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16555 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
16557 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16558 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16571 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16572 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16588 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16589 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16623 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16625 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16626 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16636 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16638 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16639 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16652 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16654 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16655 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16659 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16661 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16662 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16675 btst &nan_bit, FPSR_CC(%a6) # is NAN set?
16677 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16678 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16682 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
16684 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
16685 btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
16857 mov.b 1+EXC_OPWORD(%a6), %d1 # fetch lo opword
16872 mov.l L_SCR1(%a6),%d0 # fetch displacement
16873 add.l USER_FPIAR(%a6),%d0 # add instruction PC
16875 mov.l %d0,EXC_PC(%a6) # set new PC
16883 mov.b &fbsun_flg,SPCOND_FLG(%a6)
16919 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate
16922 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes
17007 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17009 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17010 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17025 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17027 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17028 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17040 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17042 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17043 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17048 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17050 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17051 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17065 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17067 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17068 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17080 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17082 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17083 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17098 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17100 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17101 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17113 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17115 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17116 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17121 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17123 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17124 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17138 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17140 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17141 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17153 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17155 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17156 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17171 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17173 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17174 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17186 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17187 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17201 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17202 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17238 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17240 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17241 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17252 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17254 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17255 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17267 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17269 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17270 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17275 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17277 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17278 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17290 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17292 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17293 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17298 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17300 a6) # set BSUN exc bit
17301 btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
17444 mov.b &ftrapcc_flg,SPCOND_FLG(%a6)
17452 mov.b &fbsun_flg,SPCOND_FLG(%a6)
17489 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate
17492 mov.b FPSR_CC(%a6),%d1 # fetch fp ccodes
17586 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17588 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17606 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17608 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17620 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17622 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17626 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17628 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17643 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17645 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17657 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17659 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17677 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17679 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17691 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17693 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17697 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17699 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17714 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17716 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17728 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17730 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17748 btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
17750 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17762 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17780 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17818 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17820 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17830 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17832 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17844 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17846 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17850 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17852 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17864 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17866 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
17870 btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
17872 ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
18061 btst &bsun_bit,FPCR_ENABLE(%a6) # was BSUN set?
18073 mov.b 1+EXC_OPWORD(%a6),%d1 # fetch lo opword
18099 mov.l EXC_EA(%a6),%a0 # fetch <ea>
18112 mov.l EXC_EA(%a6),%a0 # fetch <ea>
18118 mov.b 0x1+EXC_OPWORD(%a6),%d1 # fetch opword
18130 mov.l EXC_EA(%a6),%a0 # fetch <ea>
18136 mov.b 0x1+EXC_OPWORD(%a6),%d1 # fetch opword
18148 mov.b &fbsun_flg,SPCOND_FLG(%a6)
18154 mov.w &0x00a1,EXC_VOFF(%a6)
18228 mov.b 1+EXC_EXTWORD(%a6),%d1 # fetch extword
18249 btst &0x5,EXC_EXTWORD(%a6) # is it a move in or out?
18256 btst &0x4,EXC_EXTWORD(%a6) # control or predecrement?
18266 btst &0x5,EXC_SR(%a6) # user or supervisor mode?
18270 cmpi.b SPCOND_FLG(%a6),&mda7_flg # is <ea> mode -(a7)?
18288 mov.l 0x0+EXC_FP0(%a6),(%a0)+ # yes
18289 mov.l 0x4+EXC_FP0(%a6),(%a0)+
18290 mov.l 0x8+EXC_FP0(%a6),(%a0)+
18296 mov.l 0x0+EXC_FP1(%a6),(%a0)+ # yes
18297 mov.l 0x4+EXC_FP1(%a6),(%a0)+
18298 mov.l 0x8+EXC_FP1(%a6),(%a0)+
18343 mov.l %a1,L_SCR1(%a6)
18361 mov.l %a0,L_SCR1(%a6)
18383 mov.l (%a0)+,0x0+EXC_FP0(%a6) # yes
18384 mov.l (%a0)+,0x4+EXC_FP0(%a6)
18385 mov.l (%a0)+,0x8+EXC_FP0(%a6)
18391 mov.l (%a0)+,0x0+EXC_FP1(%a6) # yes
18392 mov.l (%a0)+,0x4+EXC_FP1(%a6)
18393 mov.l (%a0)+,0x8+EXC_FP1(%a6)
18537 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
18625 mov.l EXC_DREGS+0x8(%a6),%a0 # Get current a0
18629 mov.l EXC_DREGS+0xc(%a6),%a0 # Get current a1
18649 mov.l (%a6),%a0 # Get current a6
18653 mov.l EXC_A7(%a6),%a0 # Get current a7
18660 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0
18663 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value
18668 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1
18671 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value
18708 mov.l (%a6),%d0 # Get current a6
18711 mov.l %d1,(%a6) # Save incr value
18716 mov.b &mia7_flg,SPCOND_FLG(%a6) # set "special case" flag
18718 mov.l EXC_A7(%a6),%d0 # Get current a7
18721 mov.l %d1,EXC_A7(%a6) # Save incr value
18729 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0
18731 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value
18736 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1
18738 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value
18771 mov.l (%a6),%d0 # Get current a6
18773 mov.l %d0,(%a6) # Save decr value
18778 mov.b &mda7_flg,SPCOND_FLG(%a6) # set "special case" flag
18780 mov.l EXC_A7(%a6),%d0 # Get current a7
18782 mov.l %d0,EXC_A7(%a6) # Save decr value
18790 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18791 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18799 add.l EXC_DREGS+0x8(%a6),%a0 # a0 + d16
18803 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18804 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18812 add.l EXC_DREGS+0xc(%a6),%a0 # a1 + d16
18816 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18817 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18829 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18830 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18842 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18843 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18855 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18856 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18868 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18869 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18877 add.l (%a6),%a0 # a6 + d16
18881 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18882 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18890 add.l EXC_A7(%a6),%a0 # a7 + d16
18904 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18905 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18916 mov.l %d0,L_SCR1(%a6) # hold opword
18926 mov.l L_SCR1(%a6),%d2 # fetch opword
18949 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18950 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18963 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18964 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
18977 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
18978 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
18986 add.l EXC_EXTWPTR(%a6),%a0 # pc + d16
18999 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19000 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
19006 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0
19012 mov.l %d0,L_SCR1(%a6) # store opword
19022 mov.l L_SCR1(%a6),%d2 # fetch opword
19059 mov.l %d0,L_SCR1(%a6) # save d0 (opword)
19065 mov.l L_SCR1(%a6),%d5
19092 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19093 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19102 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19103 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
19123 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19124 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19133 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19134 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
19204 mov.l L_SCR1(%a6),%a0
19220 # USER_FPCR(a6) = new FPCR value #
19221 # USER_FPSR(a6) = new FPSR value #
19222 # USER_FPIAR(a6) = new FPIAR value #
19246 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits
19256 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19257 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19263 mov.l %d0,USER_FPSR(%a6) # store new FPSR to stack
19264 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19265 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19271 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack
19276 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19277 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19283 mov.l %d0,USER_FPCR(%a6) # store new FPCR to stack
19284 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19285 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19291 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack
19296 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19297 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19303 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem
19304 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19305 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19311 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem
19316 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19317 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19323 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem
19324 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19325 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19331 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem
19332 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
19333 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
19339 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to mem
19375 mov.b 1+EXC_OPWORD(%a6), %d0 # fetch opcode word
19392 mov.l EXC_EA(%a6),%a0 # return <ea>
19398 mov.b &immed_flg,SPCOND_FLG(%a6)
19399 lea ([USER_FPIAR,%a6],0x4),%a0 # no; return <ea>
19408 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
19419 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
19426 mov.l %a0,EXC_EA(%a6) # put correct <ea> on stack
19458 mov.b 1+EXC_OPWORD(%a6),%d0 # fetch opcode word
19470 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
19478 mov.l EXC_EA(%a6),%a0
19493 addi.l &0xc,EXC_DREGS+0x8(%a6)
19496 addi.l &0xc,EXC_DREGS+0xc(%a6)
19511 addi.l &0xc,EXC_A6(%a6)
19514 mov.b &mia7_flg,SPCOND_FLG(%a6)
19515 addi.l &0xc,EXC_A7(%a6)
19523 mov.l EXC_EA(%a6),%a0
19525 sub.l &0x8,EXC_EA(%a6)
19540 mov.l %a0,EXC_DREGS+0x8(%a6)
19543 mov.l %a0,EXC_DREGS+0xc(%a6)
19558 mov.l %a0,EXC_A6(%a6)
19561 mov.l %a0,EXC_A7(%a6)
19562 mov.b &mda7_flg,SPCOND_FLG(%a6)
19589 # FP_SRC(a6) = source operand in extended precision #
19590 # FP_DST(a6) = destination operand in extended precision #
19595 # FP_SRC(a6) and FP_DST(a6). If the instruction was opclass zero, load #
19625 # bfextu EXC_CMDREG(%a6){&0:&3}, %d0 # extract opclass
19631 btst &0x6,EXC_CMDREG(%a6)
19638 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension word lo
19648 bfextu EXC_CMDREG(%a6){&6:&3}, %d0 # extract dst field
19656 mov.b %d0, DTAG(%a6) # store the dst optype tag
19659 bfextu EXC_CMDREG(%a6){&3:&3}, %d0 # extract src field
19667 mov.b %d0, STAG(%a6) # store the src optype tag
19681 mov.w EXC_CMDREG(%a6),%d0 # fetch extension word
19691 bfextu EXC_CMDREG(%a6){&6:&3}, %d0 # extract dst field
19699 mov.b %d0, DTAG(%a6) # store the dst optype tag
19702 bfextu EXC_CMDREG(%a6){&3:&3}, %d0 # extract src type field
19704 bfextu EXC_OPWORD(%a6){&10:&3}, %d1 # extract <ea> mode field
19708 clr.b STAG(%a6) # either NORM or ZERO
19709 bfextu EXC_OPWORD(%a6){&13:&3}, %d1 # extract src reg field
19735 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19739 mov.b &ZERO, STAG(%a6) # set ZERO optype flag
19748 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19752 mov.b &ZERO, STAG(%a6) # set ZERO optype flag
19761 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19765 mov.b &ZERO, STAG(%a6) # set ZERO optype flag
19776 mov.l %d0,L_SCR1(%a6)
19778 lea L_SCR1(%a6), %a0 # pass: ptr to the sgl
19780 mov.b %d0, STAG(%a6) # save the src tag
19789 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19807 clr.b STAG(%a6) # either NORM or ZERO
19834 cmpi.b SPCOND_FLG(%a6),&immed_flg
19844 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19849 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO
19870 cmpi.b SPCOND_FLG(%a6),&immed_flg
19880 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19885 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO
19906 cmpi.b SPCOND_FLG(%a6),&immed_flg
19916 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19921 mov.b &ZERO, STAG(%a6) # set optype tag to ZERO
19942 cmpi.b SPCOND_FLG(%a6),&immed_flg
19946 mov.l %d0, L_SCR1(%a6) # store src op on stack
19952 lea L_SCR1(%a6), %a0 # pass: ptr to sgl src op
19954 mov.b %d0, STAG(%a6) # save src optype tag on stack
19962 fmov.s L_SCR1(%a6), %fp0 # read into %fp0;convert to xprec
19963 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
19977 clr.w FP_SRC_EX(%a6)
19980 mov.l %d0, FP_SRC_HI(%a6) # set ext hi(_mantissa)
19981 clr.l FP_SRC_LO(%a6) # set ext lo(_mantissa)
19983 clr.w FP_SRC_EX(%a6)
19986 bset &0x7, FP_SRC_EX(%a6) # set sgn of xprec value
19989 lea FP_SRC(%a6), %a0
19993 or.w %d1, FP_SRC_EX(%a6) # {sgn,exp}
19995 mov.b &NORM, STAG(%a6) # fix src type tag
20001 mov.w &0x7fff, FP_SRC_EX(%a6) # set exp of SNAN
20004 mov.l %d0, FP_SRC_HI(%a6)
20005 clr.l FP_SRC_LO(%a6)
20009 bset &0x7, FP_SRC_EX(%a6)
20024 cmpi.b SPCOND_FLG(%a6),&immed_flg
20027 lea L_SCR1(%a6), %a1 # pass: ptr to input dbl tmp space
20035 lea L_SCR1(%a6), %a0 # pass: ptr to input dbl
20037 mov.b %d0, STAG(%a6) # set src optype tag
20045 fmov.d L_SCR1(%a6), %fp0 # read into %fp0;convert to xprec
20046 fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
20050 lea L_SCR1(%a6), %a1 # pass: ptr to input dbl tmp space
20062 clr.w FP_SRC_EX(%a6)
20064 mov.l %d0, FP_SRC_HI(%a6)
20068 mov.l %d0, FP_SRC_LO(%a6)
20072 bset &0x7, FP_SRC_EX(%a6) # set sgn of xprec value
20075 lea FP_SRC(%a6), %a0
20079 or.w %d1, FP_SRC_EX(%a6) # {sgn,exp}
20081 mov.b &NORM, STAG(%a6) # fix src type tag
20087 mov.w &0x7fff, FP_SRC_EX(%a6) # set exp of SNAN
20090 mov.l %d0, FP_SRC_HI(%a6)
20094 mov.l %d0, FP_SRC_LO(%a6)
20098 bset &0x7, FP_SRC_EX(%a6)
20113 lea FP_SRC(%a6), %a1 # pass: ptr to input ext tmp space
20120 lea FP_SRC(%a6), %a0 # pass: ptr to src op
20126 mov.b %d0, STAG(%a6) # store the src optype tag
20131 mov.b %d0, STAG(%a6) # store the src optype tag
20144 lea FP_SRC(%a6),%a0 # pass ptr to src op
20149 mov.b %d0,STAG(%a6) # store the src optype tag
20154 mov.b %d0,STAG(%a6) # store the src optype tag
20210 bfextu EXC_CMDREG(%a6){&3:&3},%d1 # extract dst fmt
20232 tst.b STAG(%a6) # is operand normalized?
20244 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20246 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20250 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20259 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20278 tst.b STAG(%a6) # is operand normalized?
20290 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20292 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20296 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20305 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20324 tst.b STAG(%a6) # is operand normalized?
20336 or.w %d1,2+USER_FPSR(%a6) # save new exc,accrued bits
20339 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20343 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20352 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20376 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
20377 clr.w 2+FP_SCR0_EX(%a6) # clear reserved field
20378 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
20379 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
20386 lea FP_SCR0(%a6),%a0 # pass: src addr
20392 cmpi.b SPCOND_FLG(%a6),&mda7_flg
20400 tst.b STAG(%a6) # is operand normalized?
20406 bset &unfl_bit,FPSR_EXCEPT(%a6) # set underflow exc bit
20408 mov.b FPCR_ENABLE(%a6),%d0
20421 tst.b STAG(%a6) # is operand normalized?
20426 lea FP_SCR0(%a6),%a0
20430 andi.w &0x8000,FP_SCR0_EX(%a6) # keep only old sign
20431 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent
20432 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
20436 mov.l EXC_A6(%a6),(%a6) # fix stacked a6
20445 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack
20469 fmov.l L_SCR3(%a6),%fpcr # set FPCR
20477 or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
20480 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20484 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20493 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20504 bset &unfl_bit,FPSR_EXCEPT(%a6) # set UNFL
20506 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
20507 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
20508 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
20513 cmpi.b STAG(%a6),&DENORM # fetch src optype tag
20516 lea FP_SCR0(%a6),%a0
20520 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
20521 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
20524 lea FP_SCR0(%a6),%a0 # pass: ptr to fop
20527 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20531 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20540 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20545 mov.b FPCR_ENABLE(%a6),%d1
20559 ori.w &ovfl_inx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex
20562 ori.w &ovfinx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex/inex2
20572 mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode
20577 mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
20581 mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
20590 mov.b 1+EXC_OPWORD(%a6),%d1 # extract Dn
20595 mov.b FPCR_ENABLE(%a6),%d1
20613 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp
20614 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man)
20615 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man)
20617 fmov.l L_SCR3(%a6),%fpcr # set FPCR
20619 fmov.x FP_SCR0(%a6),%fp0 # force fop to be rounded
20632 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
20633 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
20634 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
20636 cmpi.b STAG(%a6),&DENORM # was src a DENORM?
20639 lea FP_SCR0(%a6),%a0
20643 bfins %d0,FP_SCR0_EX(%a6){&1:&15}
20650 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
20651 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
20652 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
20655 bclr &0x7,FP_SCR0_EX(%a6) # clear sign bit
20656 sne.b 2+FP_SCR0_EX(%a6) # set internal sign bit
20657 lea FP_SCR0(%a6),%a0 # pass: ptr to DENORM
20659 mov.b 3+L_SCR3(%a6),%d1
20663 mov.b 3+L_SCR3(%a6),%d1
20669 tst.b 2+FP_SCR0_EX(%a6) # is EXOP negative?
20671 bset &0x7,FP_SCR0_EX(%a6) # yes
20674 fmovm.x FP_SCR0(%a6),&0x40 # return EXOP in fp1
20683 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack
20707 fmov.l L_SCR3(%a6),%fpcr # set FPCR
20710 fmov.d %fp0,L_SCR1(%a6) # store does convert and round
20715 or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex
20717 mov.l EXC_EA(%a6),%a1 # pass: dst addr
20718 lea L_SCR1(%a6),%a0 # pass: src addr
20733 bset &unfl_bit,FPSR_EXCEPT(%a6) # set UNFL
20735 mov.w SRC_EX(%a0),FP_SCR0_EX(%a6)
20736 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6)
20737 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
20742 cmpi.b STAG(%a6),&DENORM # fetch src optype tag
20745 lea FP_SCR0(%a6),%a0
20749 lea FP_SCR0(%a6),%a0 # pass: ptr to operand
20750 mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
20753 lea FP_SCR0(%a6),%a0 # pass: ptr to fop
20755 mov.l %d0,L_SCR1(%a6)
20756 mov.l %d1,L_SCR2(%a6)
20758 mov.l EXC_EA(%a6),%a1 # pass: dst addr
20759 lea L_SCR1(%a6),%a0 # pass: src addr
20766 mov.b FPCR_ENABLE(%a6),%d1
20780 ori.w &ovfl_inx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex
20783 ori.w &ovfinx_mask,2+USER_FPSR(%a6) # set ovfl/aovfl/ainex/inex2
20793 mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode
20796 fmov.d %fp0,L_SCR1(%a6) # store to double
20798 mov.l EXC_EA(%a6),%a1 # pass: dst addr
20799 lea L_SCR1(%a6),%a0 # pass: src addr
20806 mov.b FPCR_ENABLE(%a6),%d1
20824 mov.w %d1,FP_SCR0_EX(%a6) # insert scaled exp
20825 mov.l SRC_HI(%a0),FP_SCR0_HI(%a6) # copy hi(man)
20826 mov.l SRC_LO(%a0),FP_SCR0_LO(%a6) # copy lo(man)
20828 fmov.l L_SCR3(%a6),%fpcr # set FPCR
20830 fmov.x FP_SCR0(%a6),%fp0 # force fop to be rounded
20894 mov.l %d0,L_SCR1(%a6) # put the new exp back on the stack
20898 mov.l %d1,L_SCR2(%a6) # build lower lword in memory
20901 mov.l L_SCR2(%a6),%d1
20903 mov.l L_SCR1(%a6),%d0
20967 mov.b STAG(%a6),%d0 # fetch input type
20971 btst &0x4,EXC_CMDREG(%a6) # static or dynamic?
20975 mov.b 1+EXC_CMDREG(%a6),%d1 # fetch dynamic reg
20983 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch static field
20989 lea FP_SRC(%a6),%a0 # pass: ptr to input
20995 # andi.l &0xcfff000f,FP_SCR0(%a6) # clear unused fields
20996 andi.l &0xcffff00f,FP_SCR0(%a6) # clear unused fields
21000 tst.b 3+FP_SCR0_EX(%a6)
21002 tst.l FP_SCR0_HI(%a6)
21004 tst.l FP_SCR0_LO(%a6)
21016 andi.w &0xf000,FP_SCR0(%a6)
21020 lea FP_SCR0(%a6),%a0 # pass: src addr
21026 cmpi.b SPCOND_FLG(%a6),&mda7_flg
21049 lea FP_SRC(%a6),%a0
21050 clr.w 2+FP_SRC_EX(%a6)
21056 ori.w &snaniop2_mask,FPSR_EXCEPT(%a6) # set SNAN/AIOP
21057 bset &0x6,FP_SRC_HI(%a6) # set snan bit
21076 # address register indexes start at 8). D0/D1/A0/A1/A6/A7 are on the #
21106 mov.l EXC_DREGS+0x0(%a6),%d0
21109 mov.l EXC_DREGS+0x4(%a6),%d0
21130 mov.l EXC_DREGS+0x8(%a6),%d0
21133 mov.l EXC_DREGS+0xc(%a6),%d0
21148 mov.l (%a6),%d0
21151 mov.l EXC_A7(%a6),%d0
21191 mov.l %d0,EXC_DREGS+0x0(%a6)
21194 mov.l %d0,EXC_DREGS+0x4(%a6)
21252 mov.w %d0,2+EXC_DREGS+0x0(%a6)
21255 mov.w %d0,2+EXC_DREGS+0x4(%a6)
21313 mov.b %d0,3+EXC_DREGS+0x0(%a6)
21316 mov.b %d0,3+EXC_DREGS+0x4(%a6)
21354 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
21378 iareg0: add.l %d0,EXC_DREGS+0x8(%a6)
21380 iareg1: add.l %d0,EXC_DREGS+0xc(%a6)
21390 iareg6: add.l %d0,(%a6)
21392 iareg7: mov.b &mia7_flg,SPCOND_FLG(%a6)
21395 add.l %d0,EXC_A7(%a6)
21398 addq.l &0x2,EXC_A7(%a6)
21418 # specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
21442 dareg0: sub.l %d0,EXC_DREGS+0x8(%a6)
21444 dareg1: sub.l %d0,EXC_DREGS+0xc(%a6)
21454 dareg6: sub.l %d0,(%a6)
21456 dareg7: mov.b &mda7_flg,SPCOND_FLG(%a6)
21459 sub.l %d0,EXC_A7(%a6)
21462 subq.l &0x2,EXC_A7(%a6)
21469 # load_fpn1(): load FP register value into FP_SRC(a6). #
21478 # FP_SRC(a6) = value loaded from FP register file #
21481 # Using the index in d0, load FP_SRC(a6) with a number from the #
21502 mov.l 0+EXC_FP0(%a6), 0+FP_SRC(%a6)
21503 mov.l 4+EXC_FP0(%a6), 4+FP_SRC(%a6)
21504 mov.l 8+EXC_FP0(%a6), 8+FP_SRC(%a6)
21505 lea FP_SRC(%a6), %a0
21508 mov.l 0+EXC_FP1(%a6), 0+FP_SRC(%a6)
21509 mov.l 4+EXC_FP1(%a6), 4+FP_SRC(%a6)
21510 mov.l 8+EXC_FP1(%a6), 8+FP_SRC(%a6)
21511 lea FP_SRC(%a6), %a0
21514 fmovm.x &0x20, FP_SRC(%a6)
21515 lea FP_SRC(%a6), %a0
21518 fmovm.x &0x10, FP_SRC(%a6)
21519 lea FP_SRC(%a6), %a0
21522 fmovm.x &0x08, FP_SRC(%a6)
21523 lea FP_SRC(%a6), %a0
21526 fmovm.x &0x04, FP_SRC(%a6)
21527 lea FP_SRC(%a6), %a0
21530 fmovm.x &0x02, FP_SRC(%a6)
21531 lea FP_SRC(%a6), %a0
21534 fmovm.x &0x01, FP_SRC(%a6)
21535 lea FP_SRC(%a6), %a0
21542 # load_fpn2(): load FP register value into FP_DST(a6). #
21551 # FP_DST(a6) = value loaded from FP register file #
21554 # Using the index in d0, load FP_DST(a6) with a number from the #
21575 mov.l 0+EXC_FP0(%a6), 0+FP_DST(%a6)
21576 mov.l 4+EXC_FP0(%a6), 4+FP_DST(%a6)
21577 mov.l 8+EXC_FP0(%a6), 8+FP_DST(%a6)
21578 lea FP_DST(%a6), %a0
21581 mov.l 0+EXC_FP1(%a6), 0+FP_DST(%a6)
21582 mov.l 4+EXC_FP1(%a6), 4+FP_DST(%a6)
21583 mov.l 8+EXC_FP1(%a6), 8+FP_DST(%a6)
21584 lea FP_DST(%a6), %a0
21587 fmovm.x &0x20, FP_DST(%a6)
21588 lea FP_DST(%a6), %a0
21591 fmovm.x &0x10, FP_DST(%a6)
21592 lea FP_DST(%a6), %a0
21595 fmovm.x &0x08, FP_DST(%a6)
21596 lea FP_DST(%a6), %a0
21599 fmovm.x &0x04, FP_DST(%a6)
21600 lea FP_DST(%a6), %a0
21603 fmovm.x &0x02, FP_DST(%a6)
21604 lea FP_DST(%a6), %a0
21607 fmovm.x &0x01, FP_DST(%a6)
21608 lea FP_DST(%a6), %a0
21650 fmovm.x &0x80, EXC_FP0(%a6)
21653 fmovm.x &0x80, EXC_FP1(%a6)
21735 btst &inex2_bit, FPSR_EXCEPT(%a6) # yes; was INEX2 set?
21777 mov.l FTEMP_LO(%a0), FTEMP_LO2(%a6) # make FTEMP_LO copy
21778 mov.l %d0, GRS(%a6) # place g,r,s after it
21797 mov.l GRS(%a6), %d0 # restore original g,r,s
21832 mov.b GRS(%a6), %d2
21833 or.b %d2, 3+FTEMP_LO2(%a6)
21838 bfextu FTEMP_LO2(%a6){%d0:&32}, %d0 # %d0 = new G,R,S
21886 mov.b GRS(%a6), %d2
21887 or.b %d2, 3+FTEMP_LO2(%a6)
21894 bftst FTEMP_LO2(%a6){%d0:&31} # were any bits shifted off?
21996 tst.b GRS(%a6) # were any bits shifted off?
22065 or.w &inx2a_mask, 2+USER_FPSR(%a6) # set inex2/ainex
22753 # bset &z_bit, FPSR_CC(%a6) # yes; set zero ccode bit
22763 btst &inex2_bit, FPSR_EXCEPT(%a6) # is INEX2 set?
22765 bset &aunfl_bit, FPSR_AEXCEPT(%a6) # yes; set aunfl
22813 # bset &z_bit,FPSR_CC(%a6) # yes; set zero ccode bit
22823 btst &inex2_bit,FPSR_EXCEPT(%a6) # is INEX2 set?
22825 bset &aunfl_bit,FPSR_AEXCEPT(%a6) # yes; set aunfl
22952 # FP_SRC(a6) = packed operand now as a binary FP number #
22972 lea FP_SRC(%a6),%a1 # pass: ptr to super dst
22980 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp
22988 mov.b 3+FP_SRC(%a6),%d0 # get byte 4
22991 tst.l FP_SRC_HI(%a6) # is lw 2 zero?
22993 tst.l FP_SRC_LO(%a6) # is lw 3 zero?
22997 lea FP_SRC(%a6),%a0 # pass: ptr to packed op
22999 fmovm.x &0x80,FP_SRC(%a6) # make this the srcop
23081 mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input
23082 mov.l 0x4(%a0),FP_SCR0_HI(%a6) # so we don't alter it
23083 mov.l 0x8(%a0),FP_SCR0_LO(%a6)
23085 lea FP_SCR0(%a6),%a0
23106 # ( ) a6: pointer to original bcd value
23148 # ( ) a6: pointer to original bcd value
23392 mov.l USER_FPCR(%a6),%d3 # get user's FPCR
23461 ori.w &inx1a_mask,2+USER_FPSR(%a6) # set INEX1/AINEX
23480 # FP_SCR0(a6) = bcd format result on the stack. #
23503 # loop entry A6. #
23505 # A6. Calculate LEN. #
23550 # A6. This test occurs only on the first pass. If the #
23632 mov.l (%a0),L_SCR2(%a6) # save exponent for sign check
23635 clr.b BINDEC_FLG(%a6) # clr norm/denorm flag
23636 cmpi.b STAG(%a6),&DENORM # is input a DENORM?
23658 st BINDEC_FLG(%a6) # set flag for denorm
23668 mov.l (%a0),FP_SCR1(%a6) # move input to work space
23669 mov.l 4(%a0),FP_SCR1+4(%a6) # move input to work space
23670 mov.l 8(%a0),FP_SCR1+8(%a6) # move input to work space
23671 and.l &0x7fffffff,FP_SCR1(%a6) # create abs(X)
23699 tst.b BINDEC_FLG(%a6) # check for denorm
23704 mov.w FP_SCR1(%a6),%d0 # move exp to d0
23705 mov.w &0x3fff,FP_SCR1(%a6) # replace exponent with 0x3fff
23706 fmov.x FP_SCR1(%a6),%fp0 # now fp0 has 1.f
23728 # loop entry A6. The lower word of d5 is used for ICTR.
23732 # A6. Calculate LEN.
23778 or.l &opaop_mask,USER_FPSR(%a6) # set OPERR & AIOP in USER_FPSR
23857 bfextu USER_FPCR(%a6){&26:&2},%d1 # get initial rmode bits
23861 tst.l L_SCR2(%a6) # test sign of original x
23945 tst.b BINDEC_FLG(%a6) # check for denorm
24015 # a2: x/ptr to FP_SCR1(a6)
24022 fmov.x %fp0,FP_SCR1(%a6) # move Y to memory
24023 lea.l FP_SCR1(%a6),%a2 # load a2 with ptr to FP_SCR1
24027 fmov.x FP_SCR1(%a6),%fp0 # write adjusted Y back to fpu
24037 mov.l USER_FPCR(%a6),L_SCR1(%a6) # save it for later
24038 and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
24056 # a2: ptr to FP_SCR1(a6)/Unchanged
24057 # a6: temp pointer to FP_SCR1(a6) - orig value saved and restored
24068 mov.l L_SCR1(%a6),-(%sp)
24069 mov.l L_SCR2(%a6),-(%sp)
24071 lea.l FP_SCR1(%a6),%a0 # a0 is ptr to FP_SCR1(a6)
24072 fmov.x %fp0,(%a0) # move Y to memory at FP_SCR1(a6)
24073 tst.l L_SCR2(%a6) # test sign of original operand
24077 mov.l USER_FPSR(%a6),-(%sp)
24080 fmov.l USER_FPCR(%a6),%fpcr
24082 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode
24085 fint.x FP_SCR1(%a6),%fp0 # do fint()
24087 or.w %d0,FPSR_EXCEPT(%a6)
24090 ## or.w %d0,FPSR_EXCEPT(%a6)
24092 mov.b (%sp),USER_FPSR(%a6)
24095 mov.l (%sp)+,L_SCR2(%a6)
24096 mov.l (%sp)+,L_SCR1(%a6)
24099 mov.l L_SCR2(%a6),FP_SCR1(%a6) # restore original exponent
24100 mov.l L_SCR1(%a6),USER_FPCR(%a6) # restore user's FPCR
24105 # A6. This test occurs only on the first pass. If the
24124 # a2: ptr to FP_SCR1(a6)/Unchanged
24156 tst.b BINDEC_FLG(%a6) # check if input was norm
24171 bra.w A6_str # return to A6 and recompute YINT
24184 bra.w A6_str # return to A6 and recompute YINT
24233 # a2: ptr to FP_SCR1(a6)/Unchanged
24245 lea.l FP_SCR0(%a6),%a0
24282 # Digits are stored in L_SCR1(a6) on return from BINDEC as:
24303 # a0: ptr to result string/ptr to L_SCR1(a6)
24305 # a2: ptr to FP_SCR1(a6)/Unchanged
24315 tst.b BINDEC_FLG(%a6) # check for denorm
24341 fmov.x %fp0,FP_SCR1(%a6) # store fp0 in memory
24358 lea.l L_SCR1(%a6),%a0 # a0 is ptr to L_SCR1 for exp digits
24360 mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0
24363 bfins %d0,FP_SCR0(%a6){&4:&12} # put e3:e2:e1 in FP_SCR0
24365 bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0
24368 or.l &opaop_mask,USER_FPSR(%a6) # set OPERR & AIOP in USER_FPSR
24383 # a0: ptr to L_SCR1(a6)/Unchanged
24385 # a2: ptr to FP_SCR1(a6)/Unchanged
24396 and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
24397 tst.l L_SCR2(%a6) # check sign of original mantissa
24405 bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0
24498 # A6. Test d7. If zero, the digit formed is the ms digit. If non- #
24562 # A6. Test d7 and branch.
24628 mov.w &0x0121,EXC_VOFF(%a6) # set FSLW
24635 mov.w &0x0141,EXC_VOFF(%a6) # set FSLW
24642 mov.w &0x0101,EXC_VOFF(%a6) # set FSLW
24649 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW
24656 mov.w &0x0161,EXC_VOFF(%a6) # set FSLW
24665 mov.w &0x00a1,EXC_VOFF(%a6) # set FSLW
24672 mov.w &0x00c1,EXC_VOFF(%a6) # set FSLW
24679 mov.w &0x0081,EXC_VOFF(%a6) # set FSLW
24686 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW
24693 mov.w &0x00e1,EXC_VOFF(%a6) # set FSLW
24698 mov.l USER_FPIAR(%a6),EXC_PC(%a6) # store current PC
24700 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
24701 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
24702 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
24704 unlk %a6
24728 mov.b EXC_OPWORD+0x1(%a6),%d1
24737 mov.b EXC_OPWORD+0x1(%a6),%d1
24754 sub.l %d0,EXC_DREGS+0x8(%a6) # fix stacked a0
24757 sub.l %d0,EXC_DREGS+0xc(%a6) # fix stacked a1
24772 sub.l %d0,(%a6) # fix stacked a6
24780 cmpi.b EXC_VOFF(%a6),&0x30 # move in or out?
24783 btst &0x5,EXC_SR(%a6) # user or supervisor?
Indexes created Wed Oct 22 13:09:56 GMT 2025