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13 # THE SOFTWARE is provided on an "AS IS" basis and without warranty.
14 # To the maximum extent permitted by applicable law,
18 # regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
21 # To the maximum extent permitted by applicable law,
25 # ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
27 # Motorola assumes no responsibility for the maintenance and support
28 # of the SOFTWARE.  
30 # You are hereby granted a copyright license to use, modify, and distribute the
67 # This is the main exit point for the 68060 Floating-Point
69 # routine. The operating system can do system dependent clean-up or
70 # simply execute an "rte" as with the sample code below.
79 # This is the exit point for the 060FPSP when an enabled overflow exception
80 # is present. The routine below should point to the operating system handler 
81 # for enabled overflow conditions. The exception stack frame is an overflow
82 # stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
84 # The sample routine below simply clears the exception status bit and
97 # This is the exit point for the 060FPSP when an enabled underflow exception
98 # is present. The routine below should point to the operating system handler 
99 # for enabled underflow conditions. The exception stack frame is an underflow
100 # stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
102 # The sample routine below simply clears the exception status bit and
115 # This is the exit point for the 060FPSP when an enabled operand error exception
116 # is present. The routine below should point to the operating system handler 
117 # for enabled operand error exceptions. The exception stack frame is an operand error
118 # stack frame. The FP state frame holds the source operand of the faulting
121 # The sample routine below simply clears the exception status bit and
134 # This is the exit point for the 060FPSP when an enabled signalling NaN exception
135 # is present. The routine below should point to the operating system handler 
136 # for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN
137 # stack frame. The FP state frame holds the source operand of the faulting
140 # The sample routine below simply clears the exception status bit and
153 # This is the exit point for the 060FPSP when an enabled divide-by-zero exception
154 # is present. The routine below should point to the operating system handler 
155 # for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero
156 # stack frame. The FP state frame holds the source operand of the faulting
159 # The sample routine below simply clears the exception status bit and
172 # This is the exit point for the 060FPSP when an enabled inexact exception
173 # is present. The routine below should point to the operating system handler 
174 # for enabled inexact exceptions. The exception stack frame is an inexact
175 # stack frame. The FP state frame holds the source operand of the faulting
178 # The sample routine below simply clears the exception status bit and
191 # This is the exit point for the 060FPSP when an enabled bsun exception
192 # is present. The routine below should point to the operating system handler 
193 # for enabled bsun exceptions. The exception stack frame is a bsun
196 # The sample routine below clears the exception status bit, clears the NaN
197 # bit in the FPSR, and does an "rte". The instruction that caused the 
198 # bsun will now be re-executed but with the NaN FPSR bit cleared.
214 # This is the exit point for the 060FPSP when an F-Line Illegal exception is 
215 # encountered. Three different types of exceptions can enter the F-Line exception
217 # the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
218 # _fpsp_fline() distinguishes between the three and acts appropriately. F-Line
228 # This is the exit point for the 060FPSP when an FPU disabled exception is 
229 # encountered. Three different types of exceptions can enter the F-Line exception
231 # the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
232 # _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled
235 # The sample code below enables the FPU, sets the PC field in the exception stack
236 # frame to the PC of the instruction causing the exception, and does an "rte".
237 # The execution of the instruction then proceeds with an enabled floating-point
242 	mov.l		%d0,-(%sp)		# enabled the fpu
254 # This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
255 # discovers that the trap condition is true and it should branch to the operating
256 # system handler for the trap exception vector number 7.
258 # The sample code below simply executes an "rte".
312 # The size of this section MUST be 128 bytes!!!