Lines Matching refs:VIA1
75 #define PM_SR() via_reg(VIA1, vSR)
76 #define PM_VIA_INTR_ENABLE() via_reg(VIA1, vIER) = 0x90
77 #define PM_VIA_INTR_DISABLE() via_reg(VIA1, vIER) = 0x10
78 #define PM_VIA_CLR_INTR() via_reg(VIA1, vIFR) = 0x90
445 via1_vIER = via_reg(VIA1, vIER);
448 via1_vDirA = via_reg(VIA1, vDirA);
459 via_reg(VIA1, vDirA) = via1_vDirA;
460 via_reg(VIA1, vIER) = via1_vIER;
482 via_reg(VIA1, vIER) = via1_vIER;
491 via1_vDirA = via_reg(VIA1, vDirA);
492 via_reg(VIA1, vDirA) &= 0x7f;
498 via_reg(VIA1, vDirA) = via1_vDirA;
506 via_reg(VIA1, vDirA) = via1_vDirA;
507 via_reg(VIA1, vIER) = via1_vIER;
563 via_reg(VIA1, vDirA) = via1_vDirA;
564 via_reg(VIA1, vIER) = via1_vIER;
586 PM_VIA_CLR_INTR(); /* clear VIA1 interrupt */
685 via_reg(VIA1, vACR) |= 0x0c;
686 via_reg(VIA1, vACR) &= ~0x10;
705 via_reg(VIA1, vACR) |= 0x1c;
720 via_reg(VIA1, vACR) |= 0x1c;
735 via_reg(VIA1, vACR) |= 0x1c;
763 via1_vIER &= via_reg(VIA1, vIER);
764 via_reg(VIA1, vIER) = via1_vIER;
870 via_reg(VIA1, vIER) = via1_vIER;
890 PM_VIA_CLR_INTR(); /* clear VIA1 interrupt */
1046 via_reg(VIA1, vIER) = 0x10;
1119 if ((via_reg(VIA1, vIFR) & 0x10) == 0x10)