Lines Matching defs:dmap
43 dbdma_start(dbdma_regmap_t *dmap, dbdma_command_t *commands)
50 dmap->d_intselect = 0xff; /* Endian magic - clear out interrupts */
51 DBDMA_ST4_ENDIAN(&dmap->d_control,
59 while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)
62 dmap->d_cmdptrhi = 0; /* 64-bit not yet */
63 DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr);
65 DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN));
69 dbdma_stop(dbdma_regmap_t *dmap)
71 out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |
74 while (in32rb(&dmap->d_status) &
79 dbdma_flush(dbdma_regmap_t *dmap)
81 out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
83 while (in32rb(&dmap->d_status) & (DBDMA_CNTRL_FLUSH));
87 dbdma_reset(dbdma_regmap_t *dmap)
89 out32rb(&dmap->d_control,
97 while (in32rb(&dmap->d_status) & DBDMA_CNTRL_RUN);
101 dbdma_continue(dbdma_regmap_t *dmap)
103 out32rb(&dmap->d_control,
109 dbdma_pause(dbdma_regmap_t *dmap)
111 DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE));
113 while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)