Lines Matching refs:sc_wdcdev
66 struct wdc_softc sc_wdcdev;
127 sc->sc_wdcdev.sc_atac.atac_dev = self;
128 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
154 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
207 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
208 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
210 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
211 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
212 sc->sc_wdcdev.sc_atac.atac_set_modes =
215 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
220 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3;
221 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1;
226 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing;
230 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
231 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 /*| ATAC_CAP_DATA32*/;
233 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr;
234 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
235 sc->sc_wdcdev.wdc_maxdrives = 2;
236 sc->sc_wdcdev.dma_arg = sc;
237 sc->sc_wdcdev.dma_init = wdc_obio_dma_init;
238 sc->sc_wdcdev.dma_start = wdc_obio_dma_start;
239 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish;
242 chp->ch_atac = &sc->sc_wdcdev.sc_atac;
363 sc->sc_wdcdev.select = 0;
368 sc->sc_wdcdev.select = wdc_obio_select;
430 sc->sc_wdcdev.select = 0;
435 sc->sc_wdcdev.select = wdc_obio_select;
454 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
455 sc->sc_wdcdev.regs->cmd_baseioh, WDC_REG_NPORTS << 4);
460 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot,
Indexes created Fri Oct 17 09:09:57 GMT 2025