Cross Reference: /src/sys/arch/news68k/dev/si.c

Lines Matching defs:ncr_sc
67 	struct	ncr5380_softc	ncr_sc;
163 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
167 	ncr_sc->sc_dev = self;
168 	ncr_sc->sc_regt = ha->ha_bust;
169 	if (bus_space_map(ncr_sc->sc_regt, (bus_addr_t)ha->ha_address,
170 	    ha->ha_size, 0, &ncr_sc->sc_regh) != 0) {
185 	ncr_sc->sc_no_disconnect = (sc->sc_options & SI_NO_DISCONNECT);
186 	ncr_sc->sc_parity_disable = (sc->sc_options & SI_NO_PARITY_CHK) >> 8;
188 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
190 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
191 	ncr_sc->sc_dma_alloc   = si_dma_alloc;
192 	ncr_sc->sc_dma_free    = si_dma_free;
193 	ncr_sc->sc_dma_poll    = si_dma_poll;
194 	ncr_sc->sc_dma_start   = si_dma_start;
195 	ncr_sc->sc_dma_eop     = si_dma_eop;
196 	ncr_sc->sc_dma_stop    = si_dma_stop;
200 		ncr_sc->sc_dma_alloc = NULL;
202 	ncr_sc->sci_r0 = 0;
203 	ncr_sc->sci_r1 = 1;
204 	ncr_sc->sci_r2 = 2;
205 	ncr_sc->sci_r3 = 3;
206 	ncr_sc->sci_r4 = 4;
207 	ncr_sc->sci_r5 = 5;
208 	ncr_sc->sci_r6 = 6;
209 	ncr_sc->sci_r7 = 7;
211 	ncr_sc->sc_rev = NCR_VARIANT_CXD1180;
213 	ncr_sc->sc_pio_in  = ncr5380_pio_in;
214 	ncr_sc->sc_pio_out = ncr5380_pio_out;
216 	ncr_sc->sc_adapter.adapt_minphys = minphys;
217 	ncr_sc->sc_channel.chan_id = 7;
223 	ncr5380_attach(ncr_sc);
235 	(void)ncr5380_intr(&sc->ncr_sc);
244 si_dma_alloc(struct ncr5380_softc *ncr_sc)
246 	struct sci_req *sr = ncr_sc->sc_current;
261 si_dma_free(struct ncr5380_softc *ncr_sc)
263 	struct sci_req *sr = ncr_sc->sc_current;
275 si_dma_start(struct ncr5380_softc *ncr_sc)
277 	struct si_softc *sc = (struct si_softc *)ncr_sc;
279 	struct sci_req *sr = ncr_sc->sc_current;
288 	addr = (u_int)ncr_sc->sc_dataptr;
290 	len = sc->sc_xlen = ncr_sc->sc_datalen;
316 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
317 		NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
318 		NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
325 		NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
328 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
329 		NCR5380_WRITE(ncr_sc, sci_icmd, 0);
330 		NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
337 		NCR5380_WRITE(ncr_sc, sci_irecv, 0);
340 	ncr_sc->sc_state |= NCR_DOINGDMA;
347 si_dma_poll(struct ncr5380_softc *ncr_sc)
349 	struct si_softc *sc = (struct si_softc *)ncr_sc;
364 		    device_xname(ncr_sc->sc_dev));
371 si_dma_eop(struct ncr5380_softc *ncr_sc)
378 si_dma_stop(struct ncr5380_softc *ncr_sc)
380 	struct si_softc *sc = (struct si_softc *)ncr_sc;
382 	struct sci_req *sr = ncr_sc->sc_current;
393 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
399 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
407 	NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID);
410 	if (ncr_sc->sc_state & NCR_ABORTING)
421 	ncr_sc->sc_dataptr += ntrans;
422 	ncr_sc->sc_datalen -= ntrans;
434 	NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) &
436 	NCR5380_WRITE(ncr_sc, sci_icmd, 0);