Cross Reference: /src/sys/arch/news68k/dev/si.c

Lines Matching defs:ncr_sc
67 	struct	ncr5380_softc	ncr_sc;
128 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
132 	ncr_sc->sc_dev = self;
133 	ncr_sc->sc_regt = ha->ha_bust;
134 	if (bus_space_map(ncr_sc->sc_regt, (bus_addr_t)ha->ha_address,
135 	    ha->ha_size, 0, &ncr_sc->sc_regh) != 0) {
150 	ncr_sc->sc_no_disconnect = (sc->sc_options & SI_NO_DISCONNECT);
151 	ncr_sc->sc_parity_disable = (sc->sc_options & SI_NO_PARITY_CHK) >> 8;
153 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
155 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
156 	ncr_sc->sc_dma_alloc   = si_dma_alloc;
157 	ncr_sc->sc_dma_free    = si_dma_free;
158 	ncr_sc->sc_dma_poll    = si_dma_poll;
159 	ncr_sc->sc_dma_start   = si_dma_start;
160 	ncr_sc->sc_dma_eop     = si_dma_eop;
161 	ncr_sc->sc_dma_stop    = si_dma_stop;
165 		ncr_sc->sc_dma_alloc = NULL;
167 	ncr_sc->sci_r0 = 0;
168 	ncr_sc->sci_r1 = 1;
169 	ncr_sc->sci_r2 = 2;
170 	ncr_sc->sci_r3 = 3;
171 	ncr_sc->sci_r4 = 4;
172 	ncr_sc->sci_r5 = 5;
173 	ncr_sc->sci_r6 = 6;
174 	ncr_sc->sci_r7 = 7;
176 	ncr_sc->sc_rev = NCR_VARIANT_CXD1180;
178 	ncr_sc->sc_pio_in  = ncr5380_pio_in;
179 	ncr_sc->sc_pio_out = ncr5380_pio_out;
181 	ncr_sc->sc_adapter.adapt_minphys = minphys;
182 	ncr_sc->sc_channel.chan_id = 7;
188 	ncr5380_attach(ncr_sc);
200 	(void)ncr5380_intr(&sc->ncr_sc);
209 si_dma_alloc(struct ncr5380_softc *ncr_sc)
211 	struct sci_req *sr = ncr_sc->sc_current;
226 si_dma_free(struct ncr5380_softc *ncr_sc)
228 	struct sci_req *sr = ncr_sc->sc_current;
240 si_dma_start(struct ncr5380_softc *ncr_sc)
242 	struct si_softc *sc = (struct si_softc *)ncr_sc;
244 	struct sci_req *sr = ncr_sc->sc_current;
253 	addr = (u_int)ncr_sc->sc_dataptr;
255 	len = sc->sc_xlen = ncr_sc->sc_datalen;
281 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
282 		NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
283 		NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
290 		NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
293 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
294 		NCR5380_WRITE(ncr_sc, sci_icmd, 0);
295 		NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
302 		NCR5380_WRITE(ncr_sc, sci_irecv, 0);
305 	ncr_sc->sc_state |= NCR_DOINGDMA;
312 si_dma_poll(struct ncr5380_softc *ncr_sc)
314 	struct si_softc *sc = (struct si_softc *)ncr_sc;
329 		    device_xname(ncr_sc->sc_dev));
336 si_dma_eop(struct ncr5380_softc *ncr_sc)
343 si_dma_stop(struct ncr5380_softc *ncr_sc)
345 	struct si_softc *sc = (struct si_softc *)ncr_sc;
347 	struct sci_req *sr = ncr_sc->sc_current;
358 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
364 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
372 	NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID);
375 	if (ncr_sc->sc_state & NCR_ABORTING)
386 	ncr_sc->sc_dataptr += ntrans;
387 	ncr_sc->sc_datalen -= ntrans;
399 	NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) &
401 	NCR5380_WRITE(ncr_sc, sci_icmd, 0);
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