Lines Matching refs:ESP_DCTL
398 /* @@@ Some ESP_DCTL bits probably need setting */
399 NCR_WRITE_REG(sc, ESP_DCTL,
402 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc,ESP_DCTL)));
403 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB);
405 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL)));
475 NCR_WRITE_REG(sc, ESP_DCTL,
535 NCR_WRITE_REG(sc, ESP_DCTL,
547 NCR_WRITE_REG(sc, ESP_DCTL,
553 NCR_WRITE_REG(sc, ESP_DCTL,
575 NCR_WRITE_REG(sc, ESP_DCTL,
626 NCR_WRITE_REG(sc, ESP_DCTL,
638 NCR_WRITE_REG(sc, ESP_DCTL,
680 NCR_WRITE_REG(sc, ESP_DCTL,
685 NCR_WRITE_REG(sc, ESP_DCTL,
741 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL)));
773 NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB);
774 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
1389 NCR_WRITE_REG(sc, ESP_DCTL,
1393 NCR_WRITE_REG(sc, ESP_DCTL,
1396 DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
1593 /* NCR_WRITE_REG(sc, ESP_DCTL, ctl); */
1653 NCR_WRITE_REG(sc, ESP_DCTL, ctl);
1675 NCR_WRITE_REG(sc, ESP_DCTL,
1847 NCR_WRITE_REG(sc, ESP_DCTL,
1850 NCR_WRITE_REG(sc, ESP_DCTL,
1853 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL)));
1884 NCR_WRITE_REG(sc, ESP_DCTL,
1887 NCR_WRITE_REG(sc, ESP_DCTL,
1890 DPRINTF(("esp dctl is 0x%02x\n", NCR_READ_REG(sc, ESP_DCTL)));
Indexes created Mon Oct 20 16:09:52 GMT 2025