Cross Reference: /src/sys/arch/next68k/stand/boot/scsi.c

Lines Matching defs:sr
53 short scsi_getbyte(volatile uint8_t *sr);
68     volatile uint8_t *sr;
71     sr = P_SCSI;
81     sr[ESP_DCTL]       = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET;
83     sr[ESP_DCTL]       = ESPDCTL_20MHZ | ESPDCTL_INTENB;
87     sr[NCR_CMD]        = NCRCMD_RSTCHIP;
88     sr[NCR_CMD]        = NCRCMD_NOP;
92     sr[NCR_CMD]        = NCRCMD_RSTSCSI;
97     sr[NCR_CMD]        = NCRCMD_RSTCHIP;
98     sr[NCR_CMD]        = NCRCMD_NOP;
100     sr[NCR_CFG1]       = NCRCFG1_SLOW | NCRCFG1_BUSID;
101     sr[NCR_CFG2]       = 0;
102     sr[NCR_CCF]        = 4; /* S5RCLKCONV_FACTOR(20); */
103     sr[NCR_TIMEOUT]    = 152; /* S5RSELECT_TIMEOUT(20,250); */
104     sr[NCR_SYNCOFF]    = 0;
105     sr[NCR_SYNCTP]     = 5;
107     sc->sc_intrstatus  = sr->s5r_intrstatus;
108     sc->sc_intrstatus  = sr->s5r_intrstatus;
110     sr[NCR_CFG1]       = NCRCFG1_PARENB | NCRCFG1_BUSID;
122 scsi_getbyte(volatile uint8_t *sr)
124     if ((sr[NCR_FFLAG] & NCRFIFO_FF) == 0)
129     return sr[NCR_FIFO];
158     volatile uint8_t *sr;
163     sr = P_SCSI;
172     sr[NCR_CMD]   = NCRCMD_FLUSH;
174     sr[NCR_SELID] = target;
175     sr[NCR_FIFO]  = MSG_IDENTIFY(lun, 0);
177 	sr[NCR_FIFO] = cbuf[i];
178     sr[NCR_CMD]   = NCRCMD_SELATN;
190 	    sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD;
194 	sc->sc_status     = sr[NCR_STAT];
195 	sc->sc_seqstep    = sr[NCR_STEP];
196 	sc->sc_intrstatus = sr[NCR_INTR];
253 	      sc->sc_status     = sr[NCR_STAT];
271 		  sr[NCR_CMD] = NCRCMD_FLUSH;
280 	      sr[NCR_CMD] = NCRCMD_ICCS;
281 	      sc->sc_result = scsi_getbyte(sr);
286 			sr[NCR_CMD] = NCRCMD_FLUSH;
287 			sr[NCR_CMD] = NCRCMD_TRANS;
307     volatile uint8_t *sr;
310     sr = P_SCSI;
312     msg = scsi_getbyte(sr);
324     sr[NCR_CMD]  = NCRCMD_MSGOK;
331     volatile uint8_t *sr;
334     sr = P_SCSI;
347 	sr[NCR_TCL] = 0;
348 	sr[NCR_TCM] = 1;
349 	sr[NCR_CMD] = NCRCMD_NOP;
350 	sr[NCR_CMD] = NCRCMD_DMA | NCRCMD_TRPAD;
366     sr[NCR_TCL]  = len & 0xff;
367     sr[NCR_TCM]  = len >> 8;
368     sr[NCR_CMD]  = NCRCMD_DMA | NCRCMD_NOP;
369     sr[NCR_CMD]  = NCRCMD_DMA | NCRCMD_TRANS;
384     sr[ESP_DCTL] = ESPDCTL_20MHZ|ESPDCTL_INTENB|ESPDCTL_DMAMOD|ESPDCTL_DMARD;
393     volatile uint8_t *sr;
398     sr = P_SCSI;
404     sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD;
405     resid = sr[NCR_TCM]<<8 | sr[NCR_TCL];
408     if (!(sr[NCR_FFLAG] & NCRFIFO_FF)) {
409 	    sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD
416 		    sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD
418 		    sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD
426     sr[ESP_DCTL] = ESPDCTL_20MHZ | ESPDCTL_INTENB;
427     resid = (sr[NCR_TCM]<<8) + sr[NCR_TCL];
431     DPRINTF(("DMA done. remain = %d, state = 0x%x, fifo = 0x%x.\n", resid, state, sr[NCR_FFLAG] & NCRFIFO_FF));
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