Lines Matching refs:MIPS_PHYS_TO_KSEG1
41 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
47 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
48 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
49 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */
50 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
51 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
52 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
53 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */
54 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
55 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */
80 #define D0_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
81 #define D1_REGBASE MIPS_PHYS_TO_KSEG1(0x10009000)
82 #define D2_REGBASE MIPS_PHYS_TO_KSEG1(0x1000a000)
83 #define D3_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b000)
84 #define D4_REGBASE MIPS_PHYS_TO_KSEG1(0x1000b400)
85 #define D5_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c000)
86 #define D6_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c400)
87 #define D7_REGBASE MIPS_PHYS_TO_KSEG1(0x1000c800)
88 #define D8_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d000)
89 #define D9_REGBASE MIPS_PHYS_TO_KSEG1(0x1000d400)
99 #define D0_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10008000)
100 #define D0_MADR_REG MIPS_PHYS_TO_KSEG1(0x10008010)
101 #define D0_QWC_REG MIPS_PHYS_TO_KSEG1(0x10008020)
102 #define D0_TADR_REG MIPS_PHYS_TO_KSEG1(0x10008030)
103 #define D0_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10008040)
104 #define D0_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10008050)
106 #define D1_CHCR_REG MIPS_PHYS_TO_KSEG1(0x10009000)
107 #define D1_MADR_REG MIPS_PHYS_TO_KSEG1(0x10009010)
108 #define D1_QWC_REG MIPS_PHYS_TO_KSEG1(0x10009020)
109 #define D1_TADR_REG MIPS_PHYS_TO_KSEG1(0x10009030)
110 #define D1_ASR0_REG MIPS_PHYS_TO_KSEG1(0x10009040)
111 #define D1_ASR1_REG MIPS_PHYS_TO_KSEG1(0x10009050)
113 #define D2_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000a000)
114 #define D2_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000a010)
115 #define D2_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000a020)
116 #define D2_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000a030)
117 #define D2_ASR0_REG MIPS_PHYS_TO_KSEG1(0x1000a040)
118 #define D2_ASR1_REG MIPS_PHYS_TO_KSEG1(0x1000a050)
120 #define D3_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b000)
121 #define D3_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b010)
122 #define D3_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b020)
124 #define D4_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000b400)
125 #define D4_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000b410)
126 #define D4_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000b420)
127 #define D4_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000b430)
129 #define D5_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c000)
130 #define D5_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c010)
131 #define D5_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c020)
133 #define D6_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c400)
134 #define D6_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c410)
135 #define D6_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c420)
136 #define D6_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000c430)
138 #define D7_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000c800)
139 #define D7_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000c810)
140 #define D7_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000c820)
142 #define D8_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d000)
143 #define D8_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d010)
144 #define D8_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d020)
145 #define D8_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d080)
147 #define D9_CHCR_REG MIPS_PHYS_TO_KSEG1(0x1000d400)
148 #define D9_MADR_REG MIPS_PHYS_TO_KSEG1(0x1000d410)
149 #define D9_QWC_REG MIPS_PHYS_TO_KSEG1(0x1000d420)
150 #define D9_TADR_REG MIPS_PHYS_TO_KSEG1(0x1000d430)
151 #define D9_SADR_REG MIPS_PHYS_TO_KSEG1(0x1000d480)
Indexes created Thu Oct 23 22:10:10 GMT 2025